DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The 5/5/2026 "Reply" elects without traverse and identifies claims 1-16 as being drawn to Group I, Species A. Accordingly, Examiner has withdrawn claims 17-20 from further consideration as being drawn to a non-elected invention. See, for example, 37 CFR § 1.142(b).
The 3/11/2026 restriction requirement is proper, is maintained, and is hereby made final.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 10-12, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw (US Pub. No. 2020/0105761).
Regarding claim 1, in FIGs. 6A-B, Liaw discloses a semiconductor device, comprising: a first active area layer (e.g. 635WN, paragraph [0061]) that extends in a first direction (x); a first metal (650, paragraph [0113]) over diffusion layer that extends in a second direction (y) that is different than the first direction, the first metal over diffusion layer situated over the first active area layer; a first gate (685, paragraph [0064]) that extends in the second direction and over the first active area layer; a first gate end of the first gate that abuts a first dielectric region (540/640, paragraph [0050]); and first low-k dielectric material situated in the first dielectric region (paragraph [0050]).
Regarding claim 2, in FIGs. 6A-B, Liaw discloses that the first dielectric region does not include the first gate.
Regarding claim 3, in FIGs. 6A-B, Liaw discloses that the first direction is perpendicular to the second direction.
Regarding claim 4, in FIGs. 6A-B, Liaw discloses that the first dielectric region includes a first portion having a first width and a second portion having a second width that is greater than the first width (e.g. see upper left most 640 in FIG. 6A).
Regarding claim 5, in FIGs. 6A-B, Liaw discloses that the second portion abuts the first gate at the first gate end.
Regarding claim 6, in FIGs. 6A-B, Liaw discloses that the first low-k dielectric material is situated in the second portion of the first dielectric region.
Regarding claim 7, in FIGs. 6A-B, Liaw discloses an insulation layer (690, paragraph [0064]) situated under the first active area layer and above a second active area layer that extends in the first direction.
Regarding claim 10, in FIGs. 6A-B, Liaw discloses a second active area layer (e.g. 635WP) that extends in the first direction (x), the second active area layer separated from the first active area layer in the second direction (y); a second metal over diffusion layer (650 associated with 635WP, paragraph [0113]) that extends in the second direction over the second active area layer; a second gate (685) that extends in the second direction and over the second active area layer; a second gate end of the second gate that abuts a second dielectric region (540/640, paragraph [0050]); and second low-k dielectric material situated in the second dielectric region (paragraph [0050]).
Regarding claim 11, in FIGs. 6A-B, Liaw discloses a semiconductor device, comprising: a first cell including: a first active area layer (635WN) that extends in a first direction (x); a first metal over diffusion layer (650) that extends in a second direction (y) that is perpendicular to the first direction, the first metal over diffusion layer situated over the first active area layer; a first gate (685) that extends in the second direction and over the first active area layer; and a first gate end of the first gate that abuts a first dielectric region (540/640/520); and a second cell including: a second active area layer (635WP) that extends in the first direction; a second metal over diffusion layer (650 associated with 635WP, paragraph [0113]) that extends in the second direction over the second active area layer; a second gate (685) that extends in the second direction and over the second active area layer; a second gate end of the second gate that abuts a second dielectric region (640); and a third gate end of the second gate in the second cell that abuts the first dielectric region.
Regarding claim 12, in FIGs. 6A-B, Liaw discloses that the first dielectric region includes a first portion having a first width (640) and a second portion (520) having a second width that is greater than the first width and that extends into the first cell and the second cell.
Regarding claim 15, in FIGs. 6A-B, Liaw discloses an insulation layer (690) situated under the first active area layer and above a third active area layer that extends in the first direction.
Allowable Subject Matter
Claims 8-9, 13-14, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 8-9, the prior art failed to disclose or reasonably suggest the claimed semiconductor device particularly characterized by a second metal over diffusion layer that extends in the second direction and under the second active area layer.
Regarding claim 13, the prior art failed to disclose or reasonably suggest the claimed semiconductor device particularly characterized by the second portion abuts the first gate in the first cell at the first gate end and the second gate in the second cell at the third gate end.
Regarding claim 14, the prior art failed to disclose or reasonably suggest the claimed semiconductor device particularly characterized by a low-k dielectric is situated in the second portion, in combination with the features of claim 12.
Regarding claim 16, the prior art failed to disclose or reasonably suggest the claimed semiconductor device particularly characterized by a third metal over diffusion layer that extends in the second direction and under the third active area layer, wherein the first gate extends over the third active area layer and the first dielectric region abuts the first gate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891
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