DETAILED ACTION
This action is responsive to the following communication: the response filed 4/29/26. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-18 pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/29/26 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-7, 11, 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Van Buskirk et al. (US 7,103,706 –herein Van Buskirk) in view of Mu et al. (US 2015/0085593 ‒hereinafter Mu), and further in view of Edelen et al. (US 2006/0077708 ‒hereinafter Edelen).
Regarding claim 1, Van Buskirk discloses a memory storage device, comprising:
a memory array (62; fig. 2), comprises a memory cell (64; fig. 2, detailed as memory cell 92; fig. 5) and a reference cell (66/68; fig. 2, detailed as reference cell 94/96; fig. 5), wherein the memory cell and the reference cell are erased together during an erase phase (300; fig. 11, “The program and erase routine then erases [i.e. erased together during an erase phase] the data bits [i.e. of the memory cell] and the reference bits [i.e. of the reference cell]” column/line(s): 11/66-67); and
a sensing amplifier circuit (104; fig. 5), coupled to the memory array, and the sensing amplifier circuit (104) compares the memory cell (92) with a reference current (i.e. read current of reference cell; column/line(s): 12/28-30) of programmed reference cell (94/96) to determine whether the memory cell (whether cell 92 is in a programmed or unprogrammed state; column/line(s): 9/37-41) is in a programmed state or an erase state during a reading phase (340; fig. 11), the sensing amplifier circuit (104) determines that the memory cell is in the erased state (380; fig. 11).
Van Buskirk does not expressly disclose compares a cell current with a reference current, wherein in response to that the cell current is greater than the reference current, wherein in response to the cell current being equal to the reference current, the sensing amplifier circuit determines that the memory cell is only in the programmed state.
Mu discloses compares a cell current with a reference current (“comparing the accessed cell current at a read gate voltage against a read reference current” para 0016), wherein in response to that the cell current is greater than the reference current (“when cell current is higher than the reference current, the cell is read as erased” para 0016), the sensing amplifier circuit determines that the memory cell is in the erased state (fig. 6 para 0016).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is modifiable as taught by Mu for the purpose of improving read operations by retaining a useful read margin of the device at low internal supply voltages (para 0013 of Mu), which benefits the commonly understood advantage of securing the integrity of data storage.
Edelen discloses wherein in response to the cell current (i.e. generated current from data cell; para 0019) being equal to the reference current, the sensing amplifier circuit (25; fig. 1) determines that the memory cell is only in the programmed state (“sense amplifier 25 compares the reference current to the generated current” and “when the reference current is substantially equal to the generated current (i.e., data cell 37 is programmed)” para 0019).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is further modifiable as taught by Edelen for the purpose of accurately determining a state of the device, which facilitates data accessing schemes as is consistent with known practices in the prior art (para 0006-0007 of Edelen).
Regarding claim 2, Van Buskirk discloses the memory storage device, further comprises: a controller circuit, coupled to the memory array, wherein in the erase phase (300; fig. 11), the controller is configured to perform an erase operation on the memory cell and the reference cell (i.e. “erases [i.e. erased together during an erase phase] the data bits [i.e. of the memory cell] and the reference bits [i.e. of the reference cell]” column/line(s): 11/66-67), and the controller circuit performs a programming operation on the reference cell (310; fig. 11, “programs a first bit of the reference cells” column/line(s): 12/1-2).
Regarding claim 3, Van Buskirk discloses the memory storage device, further comprises: coupled to the memory array (62; fig. 2), and during the reading phase (340; fig. 11), is configured to provide the reference current (column/line(s): 12/28-30).
Van Buskirk does not expressly disclose a reference current generating circuit.
Mu discloses a reference current generating circuit (34; fig. 1), coupled (i.e. electrically coupled) to the memory array (22; fig. 1), and during the reading phase (para 0013), the reference current generating circuit is configured to provide the reference current (Iref; fig. 5).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is modifiable as taught by Mu for the purpose of improving read operations by retaining a useful read margin of the device at low internal supply voltages (para 0013 of Mu), which benefits the commonly understood advantage of securing the integrity of data storage.
Regarding claim 5, Van Buskirk discloses the memory storage device, wherein the reference cell draws the reference current (“read currents are read from a programmed bit of a first reference cell and an erased or unprogrammed bit of a second reference cell” column/line(s): 12/28-30).
Van Buskirk does not expressly disclose from the reference current generating circuit.
Mu discloses from the reference current generating circuit (34; fig. 1, 5).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is modifiable as taught by Mu for the purpose of improving read operations by retaining a useful read margin of the device at low internal supply voltages (para 0013 of Mu), which benefits the commonly understood advantage of securing the integrity of data storage.
Regarding claim 6, Van Buskirk does not expressly disclose the memory storage device, wherein the memory cell draws the cell current from the sensing amplifier circuit.
Mu discloses wherein the memory cell draws the cell current from the sensing amplifier circuit (the memory cell 24 draws cell current Ids from sensing amplifier circuit 82; fig. 6).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is modifiable as taught by Mu for the purpose of improving read operations by retaining a useful read margin of the device at low internal supply voltages (para 0013 of Mu), which benefits the commonly understood advantage of securing the integrity of data storage.
Regarding claim 7, Van Buskirk discloses the memory storage device, wherein the reference cell is programmed (310; fig. 11) during a wafer test phase or after each erase operation (300; fig. 11).
Regarding claim 11, Van Buskirk discloses a reading method for a memory storage device, wherein the memory storage device comprises a memory array (62; fig. 2), and the memory array comprises a memory cell (64; fig. 2, detailed as memory cell 92; fig. 5) and a reference cell (66/68; fig. 2, detailed as reference cell 94/96; fig. 5), the reading method comprises:
during an erase phase (300; fig. 11), performing an erase operation on the memory cell and the reference cell (“The program and erase routine then erases [i.e. erased together during an erase phase] the data bits [i.e. of the memory cell] and the reference bits [i.e. of the reference cell]” column/line(s): 11/66-67);
performing a programming operation (310; fig. 11) on the reference cell (“programs a first bit of the reference cells of a reference cell” column/line(s): 12/1-2); and
during a reading phase (340; fig. 11), comparing the memory cell (92) with a reference current (i.e. read current of reference cell; column/line(s): 12/28-30) of the programmed reference cell (94/96) to determine whether the memory cell is in a programmed state or an erase state (whether cell 92 is in a programmed or unprogrammed state; column/line(s): 9/37-41; further 380; fig. 11), determining that the memory cell is in the erased state (380).
Van Buskirk does not expressly disclose compares a cell current with a reference current, wherein in response to the cell current is being greater than the reference current, wherein in response to the cell current being equal to the reference current, determining that the memory cell is only in the programmed state.
Mu discloses compares a cell current with a reference current (“comparing the accessed cell current at a read gate voltage against a read reference current” para 0016), wherein in response to the cell current is being greater than the reference current, determining that the memory cell is in the erased state (“when cell current is higher than the reference current, the cell is read as erased” para 0016).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is modifiable as taught by Mu for the purpose of improving read operations by retaining a useful read margin of the device at low internal supply voltages (para 0013 of Mu), which benefits the commonly understood advantage of securing the integrity of data storage.
Edelen discloses wherein in response to the cell current (i.e. generated current from data cell; para 0019) being equal to the reference current, the sensing amplifier circuit (25; fig. 1) determines that the memory cell is only in the programmed state (“sense amplifier 25 compares the reference current to the generated current” and “when the reference current is substantially equal to the generated current (i.e., data cell 37 is programmed)” para 0019).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is further modifiable as taught by Edelen for the purpose of accurately determining a state of the device, which facilitates data accessing schemes as is consistent with known practices in the prior art (para 0006-0007 of Edelen).
Regarding claim 13, Van Buskirk discloses the reading method for the memory storage device, wherein the reference cell draws the reference current (“read currents are read from a programmed bit of a first reference cell and an erased or unprogrammed bit of a second reference cell” column/line(s): 12/28-30).
Van Buskirk does not expressly disclose from a reference current generating circuit.
Mu discloses from a reference current generating circuit (34; fig. 1, 6).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is modifiable as taught by Mu for the purpose of improving read operations by retaining a useful read margin of the device at low internal supply voltages (para 0013 of Mu), which benefits the commonly understood advantage of securing the integrity of data storage.
Regarding claim 14, Van Buskirk does not expressly disclose the reading method for the memory storage device, wherein the memory cell draws the cell current from a sensing amplifier circuit.
Mu discloses wherein the memory cell draws the cell current from a sensing amplifier circuit (the memory cell 24 draws cell current Ids from sensing amplifier circuit 82; fig. 6).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is modifiable as taught by Mu for the purpose of improving read operations by retaining a useful read margin of the device at low internal supply voltages (para 0013 of Mu), which benefits the commonly understood advantage of securing the integrity of data storage.
Regarding claim 15, Van Buskirk discloses the reading method for the memory storage device, wherein the reference cell is programmed (310; fig. 11) during a wafer test phase or after each erase operation (300; fig. 11).
Claim(s) 4, 8-9, 12, 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Van Buskirk et al. (US 7,103,706 –herein Van Buskirk) in view of Mu et al. (US 2015/0085593 ‒hereinafter Mu), in view of Edelen et al. (US 2006/0077708 ‒hereinafter Edelen), and further in view of Lo Giudice et al. (US 2011/0069554 ‒hereinafter Lo Giudice).
Regarding claim 4, Van Buskirk, as modified, does not expressly disclose the memory storage device, wherein the reference current generating circuit provides the reference current to the sensing amplifier circuit corresponding to the memory cell through a current mirror circuit.
Lo Giudice discloses the memory storage device, wherein the reference current generating circuit provides the reference current to the sensing amplifier circuit corresponding to the memory cell through a current mirror circuit (12; fig. 2, para 0047, further para 0058).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is further modifiable as taught by Lo Giudice for the purpose of facilitating data accessing schemes by improving read operations of the device at low internal supply voltages (para 0030 Lo Giudice), which benefits the commonly understood advantage of higher performance speeds.
Regarding claim 8, Van Buskirk discloses the memory storage device, wherein the sensing amplifier circuit comprises a sensing node (fig. 5).
Van Buskirk, as modified, does not expressly disclose the sensing node is charged to a first voltage during a precharge phase.
Lo Giudice discloses wherein the sensing amplifier circuit comprises a sensing node (sense amplifier input node In_mat; fig. 2), and the sensing node is charged (para 0063-0064) to a first voltage (first voltage as determined by precharging voltage Vcasc; fig. 2) during a precharge phase (precharging stage; para 0058, 0063-0064).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is further modifiable as taught by Lo Giudice for the purpose of facilitating data accessing schemes by improving read operations of the device at low internal supply voltages (para 0030 Lo Giudice), which benefits the commonly understood advantage of higher performance speeds.
Regarding claim 9, Van Buskirk discloses the memory storage device (fig. 11).
Van Buskirk, as modified, does not expressly disclose in response to that the cell current is equal to the reference current a voltage value of the sensing node remains at the first voltage.
Lo Giudice discloses wherein in response to that the cell current is equal to the reference current (“where the currents to be compared are exactly equal” para 0066) a voltage value of the sensing node remains at the first voltage (voltage value of the sensing node remains at first voltage as determined by Vcasc; para 0063-0064).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is further modifiable as taught by Lo Giudice for the purpose of facilitating data accessing schemes by improving read operations of the device at low internal supply voltages (para 0030 Lo Giudice), which benefits the commonly understood advantage of higher performance speeds.
Regarding claim 12, Van Buskirk, as modified, does not expressly disclose the reading method the memory storage device, further comprises: providing the reference current by current mirroring.
Lo Giudice discloses providing the reference current by current mirroring (12; fig. 2, para 0047, further para 0058).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is further modifiable as taught by Lo Giudice for the purpose of facilitating data accessing schemes by improving read operations of the device at low internal supply voltages (para 0030 Lo Giudice), which benefits the commonly understood advantage of higher performance speeds.
Regarding claim 16, Van Buskirk discloses the reading method the memory storage device, wherein the sensing amplifier circuit comprises a sensing node (fig. 5).
Van Buskirk, as modified, does not expressly disclose the reading method further comprises: charging the sensing node to a first voltage during a precharge phase.
Lo Giudice discloses the reading method further comprises: charging the sensing node to a first voltage (first voltage as determined by precharging voltage Vcasc; fig. 2) during a precharge phase (precharging stage; para 0058, 0063).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is further modifiable as taught by Lo Giudice for the purpose of facilitating data accessing schemes by improving read operations of the device at low internal supply voltages (para 0030 Lo Giudice), which benefits the commonly understood advantage of higher performance speeds.
Regarding claim 17, Van Buskirk discloses the reading method for the memory storage device (fig. 11).
Van Buskirk, as modified, does not expressly disclose in response to that the cell current is equal to the reference current a voltage value of the sensing node remains at the first voltage.
Lo Giudice discloses wherein in response to that the cell current is equal to the reference current (“where the currents to be compared are exactly equal” para 0066), a voltage value of the sensing node remains at the first voltage (voltage value of the sensing node remains at first voltage as determined by Vcasc; para 0063-0064).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is further modifiable as taught by Lo Giudice for the purpose of facilitating data accessing schemes by improving read operations of the device at low internal supply voltages (para 0030 Lo Giudice), which benefits the commonly understood advantage of higher performance speeds.
Claim(s) 8, 10, 16, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Van Buskirk et al. (US 7,103,706 –herein Van Buskirk) in view of Mu et al. (US 2015/0085593 ‒hereinafter Mu), in view of Edelen et al. (US 2006/0077708 ‒hereinafter Edelen), and further in view of Kim et al. (US 2014/0056074 ‒hereinafter Kim).
Regarding claim 8, Van Buskirk discloses the memory storage device, wherein the sensing amplifier circuit comprises a sensing node (fig. 5).
Van Buskirk, as modified, does not expressly disclose the sensing node is charged to a first voltage during a precharge phase.
Kim discloses the sensing node (S0; fig. 2) is charged to a first voltage (“sensing node S0 is precharged when the voltage V1 is applied to the voltage providing transistor VT” para 0057) during a precharge phase (precharging period t1; fig. 3).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is further modifiable as taught by Kim for the purpose of facilitating data accessing schemes and improving read operations of the device by compensating for characteristic fluctuations of a selected memory cell (para 0042 of Kim), which benefits the commonly understood advantage of securing integrity of data storage.
Regarding claim 10, Van Buskirk discloses the memory storage device, wherein in response to that the memory cell is in the erased state (para 0066).
Van Buskirk, as modified, does not expressly disclose the voltage value of the sensing node drops to a second voltage, where the second voltage is less than the first voltage.
Kim discloses the voltage value of the sensing node (“a voltage level of the sensing node S0” para 0059) drops to a second voltage (“the voltage level of the sensing node may be decreased [i.e. to a second voltage]” para 0059), where the second voltage is less than the first voltage (decreasing to the second voltage is essentially less than the voltage level; fig. 3).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is further modifiable as taught by Kim for the purpose of facilitating data accessing schemes and improving read operations of the device by compensating for characteristic fluctuations of a selected memory cell (para 0042 of Kim), which benefits the commonly understood advantage of securing integrity of data storage.
Regarding claim 16, Van Buskirk discloses the reading method for the memory storage device, wherein the sensing amplifier circuit comprises a sensing node (fig. 5).
Van Buskirk, as modified, does not expressly disclose charging the sensing node to a first voltage during a precharge phase.
Kim discloses charging the sensing node (S0; fig. 2) to a first voltage (“sensing node S0 is precharged when the voltage V1 is applied to the voltage providing transistor VT” para 0057) during a precharge phase (precharging period t1; fig. 3).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is further modifiable as taught by Kim for the purpose of facilitating data accessing schemes and improving read operations of the device by compensating for characteristic fluctuations of a selected memory cell (para 0042 of Kim), which benefits the commonly understood advantage of securing integrity of data storage.
Regarding claim 18, Van Buskirk discloses the reading method for the memory storage device, wherein in response to that the memory cell is in the erased state (para 0066).
Van Buskirk, as modified, does not expressly disclose the voltage value of the sensing node drops to a second voltage, where the second voltage is less than the first voltage.
Kim discloses the voltage value of the sensing node (“a voltage level of the sensing node S0” para 0059) drops to a second voltage (“the voltage level of the sensing node may be decreased [i.e. to a second voltage]” para 0059), where the second voltage is less than the first voltage (decreasing to the second voltage is essentially less than the voltage level; fig. 3).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Van Buskirk is further modifiable as taught by Kim for the purpose of facilitating data accessing schemes and improving read operations of the device by compensating for characteristic fluctuations of a selected memory cell (para 0042 of Kim), which benefits the commonly understood advantage of securing integrity of data storage.
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/UYEN SMET/
Primary Examiner, Art Unit 2824
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