DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Group I (claims 1-9) in the reply filed on 04/10/2026 is acknowledged. The traversal is on the ground(s) that claim 10 has been amended to include each and every limitation of claim 1. This is found persuasive and the restriction requirement between Group I and Group II of the original restriction has been withdrawn. The restriction of Group III method claims (16-20) is currently maintained; however, these claims will be considered for rejoinder upon the allowance of product claims 1 and/or 10.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/29/2023 and 02/17/2025 has been considered by the examiner.
Claim Objections
Claims 5, 6, 8, 12, and 15 are objected to because of the following informalities:
Re claim 5, the Examiner suggests replacing “wherein a bottommost first conductive feature is in physical contact with a topmost second conductive feature” with “wherein a bottommost first conductive feature of the first conductive features is in physical contact with a topmost second conductive feature of the second conductive features” to provide proper antecedent basis and constancy throughout the claim.
Re claim 6, the Examiner suggests replacing “wherein a topmost dielectric layer is in physical contact with a bottommost seed layer” with “wherein a topmost dielectric layer of the dielectric layers is in physical contact with a bottommost seed layer” to provide proper antecedent basis and constancy throughout the claim.
Re claim 8, the Examiner suggests replacing “…the corresponding first conductive feature…” with “…a corresponding first conductive feature…” to provide proper antecedent basis and constancy throughout the claim.
Re claim 12, the Examiner suggests replacing “…a topmost first conductive pattern…” with “…a topmost first conductive pattern of the first conductive patterns…” to provide proper antecedent basis and constancy throughout the claim.
Re claim 15, the Examiner suggests replacing “…a topmost first diamond layer…” with “…a topmost first diamond layer of the first diamond layers…” to provide proper antecedent basis and constancy throughout the claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-9 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of copending Application No. 18/391,453 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because a “seed layer” could reasonably interpreted as an “adhesive layer” as the seed layer helps adhere the heat dissipation layer to the substrate; therefore, the scope of the claimed limitations of the instant application is similar to that of the claimed limitations of the co-pending reference application such that they are not patently distinct from each other.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
18/399,748 (Instant Application)
18/391,453 (Co-pending Reference Application)
1) An integrated circuit, comprising:
a semiconductor substrate; and
an interconnect structure disposed on the semiconductor substrate, comprising:
a signal transmission structure; and
a heat dissipation structure disposed on the signal transmission structure, comprising:
composite dielectric layers, wherein each of the composite dielectric layers comprises a seed layer and a heat dissipation layer disposed on the seed layer; and
first conductive features embedded in the composite dielectric layers.
3) wherein the material of the seed layers comprises cubic boron nitride and the material of the heat dissipation layers comprises diamond.
1) An integrated circuit, comprising:
a semiconductor substrate; and
an interconnect structure disposed on the semiconductor substrate, comprising:
a signal transmission structure; and
a heat dissipation structure disposed on the signal transmission structure, comprising:
a composite dielectric layer, comprising an adhesive layer and a diamond layer disposed on the adhesive layer; and
first conductive features embedded in the composite dielectric layer.
2) wherein the signal transmission structure comprises: dielectric layers, wherein a material of the dielectric layers is different from a material of the seed layers and a material of the heat dissipation layers; and second conductive features embedded in the dielectric layers.
2) wherein the signal transmission structure comprises: dielectric layers, wherein a material of the dielectric layers is different from materials of the composite dielectric layer; and second conductive features embedded in the dielectric layers.
4) further comprising transistors disposed on the semiconductor substrate, wherein the first conductive features are electrically connected to the transistors through the second conductive features.
3) further comprising transistors disposed on the semiconductor substrate, wherein the first conductive features are electrically connected to the transistors through the second conductive features.
5) wherein a bottommost first conductive feature is in physical contact with a topmost second conductive feature.
4) wherein a bottommost first conductive feature is in physical contact with a topmost second conductive feature.
6) wherein a topmost dielectric layer is in physical contact with a bottommost seed layer.
5) wherein a topmost dielectric layer is in physical contact with a bottommost adhesive layer.
7) wherein a number of the dielectric layers is four or more.
6) wherein a number of the dielectric layers is four or more.
8) wherein a top surface of each of the heat dissipation layers is coplanar with a top surface of the corresponding first conductive feature.
7) wherein a top surface of each of the diamond layers is coplanar with a top surface of the corresponding first conductive feature.
9) wherein the first conductive features comprise: conductive patterns extending horizontally; and conductive vias extending vertically to connect the conductive patterns located at different level heights, wherein each of the conductive patterns penetrates through one of the composite dielectric layers while each of the conductive vias penetrates through another one of the composite dielectric layers.
8) wherein the first conductive features comprise: conductive vias extending vertically to penetrate through the composite dielectric layer.
1) 1) An integrated circuit, comprising:
a semiconductor substrate; and
an interconnect structure disposed on the semiconductor substrate, comprising:
a signal transmission structure; and
a heat dissipation structure disposed on the signal transmission structure, comprising:
composite dielectric layers, wherein each of the composite dielectric layers comprises a seed layer and a heat dissipation layer disposed on the seed layer; and
first conductive features embedded in the composite dielectric layers.
2) wherein the signal transmission structure comprises: dielectric layers, wherein a material of the dielectric layers is different from a material of the seed layers and a material of the heat dissipation layers; and second conductive features embedded in the dielectric layers.
3) wherein the material of the seed layers comprises cubic boron nitride and the material of the heat dissipation layers comprises diamond.
9) An integrated circuit, comprising:
a semiconductor substrate; and
an interconnect structure disposed on the semiconductor substrate, comprising:
dielectric layers;
adhesive layers and heat dissipation layers alternately stacked on one another above the dielectric layers;
first conductive patterns and first conductive vias embedded in the dielectric layers; and
second conductive patterns and second conductive vias embedded in the adhesive layers and the heat dissipation layers, wherein the first conductive patterns, the first conductive vias, the second conductive patterns, and the second conductive vias are electrically connected to one another.
11) wherein a material of the dielectric layers is different from a material of the adhesive layer and a material of the heat dissipation layer.
12) wherein the material of the heat dissipation layer comprises diamond.
7) wherein a number of the dielectric layers is four or more.
10) wherein a number of the dielectric layers is four or more.
9) wherein the first conductive features comprise: conductive patterns extending horizontally; and conductive vias extending vertically to connect the conductive patterns located at different level heights, wherein each of the conductive patterns penetrates through one of the composite dielectric layers while each of the conductive vias penetrates through another one of the composite dielectric layers.
13) wherein each of the second conductive patterns penetrates through one of the adhesive layers and one of the heat dissipation layers, and each of the second conductive vias penetrates through another one of the adhesive layers and another one of the heat dissipation layers.
Claims 10-15 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of co-pending Application No. 18/391,453 in view of Chiou (US Pub. 2007/0224776.
Co-pending application teaches the components of the claimed first circuit and/or second circuit as shown above.
Co-pending application does not teach the concept of stacking essentially identical circuit components through “a bonding layer sandwiched between the first circuit component and the second circuit component; and through vias penetrating through the second circuit component, the bonding layer, the first seed layers, and the first diamond layers”.
Chiou teaches (Fig. 8) a stacked first circuit component and a second circuit component with a bonding layer (Fig. 5; para. 0032) sandwiched between the first circuit component and the second circuit component; and through vias (62) penetrating through the second circuit component, the bonding layer, and the metallization areas (66) (para. 0038).
It would have been obvious to one of ordinary skill in the art at the time of filing to stack the circuit component of the co-pending application claims as taught by Chiou to arrive at the instant claims for the purpose of forming a 3D integrated circuit thereby providing more components to be integrated into a given area (Chiou para. 0002).
This is a provisional nonstatutory double patenting rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM.
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/MOLLY K REIDA/Examiner, Art Unit 2899
Prosecution Insights