DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed 5/11/2026.
Claims 14-33 are pending. Claims 1-13 are cancelled. Claims 21-33 are new. Claims 14, 21 and 28 are independent.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/26/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention II and Species I in the reply filed on 5/11/2026 is acknowledged.
Claims 1-13, which have been canceled, were drawn to a nonelected Invention/Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/11/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 27 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 27 recites the limitation “the sidewalls of the substrate” in lines 2-3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14 and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uchida et al. (US 2014/0054774 A1, hereinafter “Uchida”).
Regarding independent claim 14, Uchida discloses a method of forming an integrated device, comprising:
forming a shallow trench isolation (STI) region 12 (“insulation film”- ¶0035) on a substrate 10 (“substrate”- ¶0035) having a first side and a second side, the STI region 12 being formed on the second side of the substrate 10 and forming a continuous loop around a semiconductor region (i.e., the portion of 10 within 12) (see Figs. 14A-14B);
etching a first opening 17 (“hole”- ¶0067) from the first side of the substrate 10 to the second side of the substrate 10, the first opening 17 both extending through the semiconductor region and being spaced from the STI region 12 by the semiconductor region, since the top portion of region 12 is spaced apart from opening 17 by a portion of 10 (see Figs. 15A-15B); and
filling the first opening 17 with a conductive material (i.e., “copper”- ¶0037) to form a through substrate via (TSV) 41 (“silicon through structure”- ¶0060) (see Fig. 13).
Regarding independent claim 21, Uchida discloses a method of forming an integrated device, comprising:
etching a first opening 11 (“trenches”- ¶0048) into a substrate 10 (“substrate”- ¶0035) having a first side and a second side, wherein the first opening 11 is etched into the second side of the substrate 10 (see Figs. 5A-5B);
forming a shallow trench isolation (STI) region 12 (“insulation film”- ¶0035) in the first opening 11, wherein the STI region 12 separates a first section (i.e., the portion of 10 within 12) of the second side of the substrate 10 from a second section (i.e., the portion of 10 outside 12) of the second side of the substrate 10 (see Figs. 6A-6B and 14A-14B);
forming a layer 13 (“gate insulation film”- ¶0039) comprising an insulative material over the first section of the second side of the substrate 10 and the STI region 12 (see Figs. 7A-7B and 14A-14B);
etching a second opening 17 (“hole”- ¶0067) extending from the first side of the substrate 10 to the layer 13 comprising the insulative material, wherein the first section of the second side of the substrate 10 extends between the second opening 17 and the STI region 22, since the top portion of region 12 is spaced apart from opening 17 by a portion of 10 (see Figs. 15A-15B); and
filling the second opening 17 with a conductive material (i.e., “copper”- ¶0037) to form a through substrate via (TSV) 41 (“silicon through structure”- ¶0060) (see Fig. 13).
Regarding claim 22, Uchida discloses wherein the etching of the second opening 17 exposes a side of the layer 13 comprising the insulative material that faces the substrate 10 (see Figs. 15A-15B).
Regarding claim 23, Uchida discloses the method further comprising forming a first insulative layer 18 (“insulation film”- ¶0036) after etching the second opening 17, wherein the first insulative layer 18 extends into the second opening 17 and covers sidewalls of the substrate 10 and the side of the layer 13 comprising the insulative material exposed within the second opening 17 (see Fig. 16).
Allowable Subject Matter
Claims 15-20 and 24-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 15, the prior art of record including Uchida, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “[the] method… further comprising: forming a first wire level on the second side of the substrate before the first opening is etched; and etching a second opening at a bottom of the first opening, such that etching the second opening exposes a first wire of the first wire level; and forming a second wire level on the second side of the substrate after the TSV is formed, such that the TSV is coupled to a second wire of the second wire level”.
Regarding claim 16 (which claims 17-18 depend from), the prior art of record including Uchida, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “[the] method… further comprising: forming a resist protective oxide (RPO) on the second side of the substrate after forming the STI region around the semiconductor region; forming a contact etch stop layer (CESL) on the RPO; forming a first wire level in an interlayer dielectric (ILD); and after the first opening is formed, etching a second opening at a bottom of the first opening, the second opening extending through the RPO, the CESL, and the ILD to reach the first wire level”.
Regarding claim 19, the prior art of record including Uchida, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein a sidewall of the STI region forming the continuous loop surrounding the semiconductor region has a circular profile when viewed from a top down top-down perspective”.
Regarding claim 20, the prior art of record including Uchida, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the STI region forms a second continuous loop around a second semiconductor region, and further comprising: etching a second opening through the substrate concurrently with the etching of the first opening, wherein the second opening extends through the substrate and the second semiconductor region; forming a first insulative layer lining the first opening and the second opening, extending between the first opening and the second opening on the first side of the substrate; and filling the second opening with the conductive material to form a second TSV”.
Regarding claim 24 (which claim 25 depends from), the prior art of record including Uchida, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “[the] method… further comprising: forming a wire over the layer comprising the insulative material before etching the second opening; and etching a third opening in the layer comprising the insulative material after etching the second opening, wherein the third opening exposes a surface of the wire facing the substrate, and wherein the first section of the second side of the substrate is between the third opening and the STI region”.
Regarding claim 26, the prior art of record including Uchida, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “[the] method… further comprising: forming a high-k layer comprising a high-k material on the first side of the substrate after forming the layer comprising the insulative material on the second side of the substrate, wherein after etching the second opening, sidewalls of the high-k material are exposed within the second opening; and forming a first insulative layer after etching the second opening, wherein the first insulative layer covers the sidewalls of the high-k layer exposed within the second opening”.
Claim 27 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 27, the prior art of record including Uchida, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the high-k material is a polymer, wherein the etching of the second opening results in polymer residue on the sidewalls of the substrate surrounding the second opening, wherein forming the TSV further comprises forming a seed layer within the second opening using a tool, and wherein the tool used for forming the seed layer is separated from the polymer residue by the first insulative layer”.
Claims 28-33 are allowed.
Regarding independent claim 28, Uchida discloses a method of forming an integrated device, comprising:
forming a shallow trench isolation (STI) region 12 (“insulation film”- ¶0035) on a substrate 10 (“substrate”- ¶0035), wherein the STI region 12 comprises an inner sidewall surrounding a semiconductor region (i.e., the portion of 10 within 12) (see Figs. 14A-14B);
etching an opening 17 (“hole”- ¶0067) extending through the substrate 10, wherein the opening 17 is spaced from the STI region 12 by the semiconductor region, and wherein the opening 17 exposes second sidewalls of the substrate 10 (see Figs. 15A-15B); and
forming a first insulative layer 18 (“insulation film”- ¶0036) over the second sidewalls of the substrate 10 (see Fig. 16).
Uchida does not expressly disclose forming a high-k layer on a first side of the substrate opposite the STI region, etching the opening extending through the high-k layer, and wherein the opening exposes first sidewalls of the high-k layer, forming the first insulative layer over the first sidewalls of the high-k layer, and using a tool to form a seed layer within the opening, wherein the tool is separated from the first sidewalls and the second sidewalls by the first insulative layer.
Thus, regarding independent claim 28, the claim is allowed, because the prior art of record including Uchida, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “forming a high-k layer on a first side of the substrate opposite the STI region”, “etching an opening extending through the high-k layer and the substrate, wherein the opening is spaced from the STI region by the semiconductor region, and wherein the opening exposes first sidewalls of the high-k layer and second sidewalls of the substrate”, “forming a first insulative layer over the first sidewalls of the high-k layer and the second sidewalls of the substrate” and “using a tool to form a seed layer within the opening, wherein the tool is separated from the first sidewalls and the second sidewalls by the first insulative layer”.
Claims 29-33 are allowed as being dependent on allowed claim 28.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hurwitz et al. (US 2014/0054743 A1), which discloses a method comprising forming through substrate via within an isolation structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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/JAY C CHANG/Primary Examiner, Art Unit 2817
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