DETAILED ACTION
This is the Office action based on the 18400440 application filed December 29, 2023, and in response to applicant’s argument/remark filed on April 21, 2026. Claims 1-17 and 21-23 are currently pending and have been considered below. Applicant’s cancellation of claims 18-20 acknowledged.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election, without traverse, of the invention of Group I, claims 1-17 in the reply filed on April 21, 2026 is acknowledged. Claims 18-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 6 rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 6 recites “wherein a likelihood of a degradation in a pick force used to remove the semiconductor die is reduced based on a step height from a surface of the recess to a top surface of the interconnect pad structure” (emphasis added), but fails to specify the basis for the reduction, i.e. reduced from what ? What is the likelihood of a degradation to compare to ? For the purpose of examining it will be assumed that the likelihood of a degradation is reduced when compare to any step height.
Claim 7 rejected under 35 U.S.C. 112(b) because they are directly or indirectly dependent on claim 6.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 8-11, 13-17 and 21-23 rejected under 35 U.S.C. 103 as being unpatentable over Arvin et al. (U.S. PGPub. No. 20170062291), hereinafter “Arvin”, in view of Matsunaga et al. (U.S. PGPub. No. 20030205814), hereinafter “Matsunaga”, and Lien et al. (U.S. Pat. No. 5834125), hereinafter “Lien”.--Claim 1: Arvin teaches a method of forming a temporary test structure for an integrated circuit ([0002]), comprisinga) providing a substrate comprising active or operable portion of a semiconductor device, covered by a dielectric layer 100, such as silicon oxide, and a plurality of conductive interconnect 200, containing Al, Cu, W or a metal alloy (Fig. 2, Step 110 in Fig. 1, [0043]);b) optionally providing an insulating polymer layer 300, such as photoresist or polyimide, on the dielectric layer 100 (Fig. 2, [0043]);c) forming a test structure 400, comprising a conductive layer over a barrier layer over the dielectric layer 100 (Fig. 3, [0044]);d) forming a photoresist layer on the test layer 400 (Fig. 4, [0045]);e) exposing and developing the photoresist layer to form a patterned photoresist layer 500 (Fig. 4, [0045]);f) forming conductive bumps 600, such as Cu, Al, Ni,…, in the openings in the patterned photoresist layer 500 (Fig. 5, [0045]);g) stripping off the patterned photoresist layer 500 (Fig. 6, [0045]);h) patterning the test structure 400 by selectively removing a portion of the test layer 400 by using a lithographic process then RIE or chemical wet etching, or by irradiating a laser through a mask, to form a pattern of test pads and electrical connections (Fig. 7 and 8, [0046]);i) performing an electrical test for the integrated circuit (Fig. 9, [0047-0048]);j) removing at least 65% or all of the test structure 400 (Fig. 10, [0049]), then continuing a normal processing step. It would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to form the conductive interconnect 200 and the conductive layer in the test structure to be the same conductive material, such as aluminum, in the invention of Arvin to simplify manufacturing process. Since Arvin teaches that the selectively removing a portion of the test layer 400, i.e. step (h), may be performed by a lithographic process then RIE or chemical wet etching, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to etch the portion of the test layer 400 in a single step of wet chemical etching. Arvin further teach that the testing may be performed before the forming of the conductive bumps, in which case all of the test structure 400 is removed ([0049]). It is noted that this would eliminate steps d)-g). Arvin is silent about the normal processing step. Matsunaga, also directed to fabricating a semiconductor integrated circuit, teaches that after forming a conductive interconnect 42 (Fig. 5A, [0078]), a next interconnection level may be formed by forming a passivation layer 21 having a through hole 22 on the conductive interconnect 42 ([0078, 0073]), then depositing a TaN barrier film on the conductive interconnect 42, then depositing an Al film on the TaN barrier film ([0079]), then removing the TaN barrier film and the Al film outside the through hole to form an Al pad 44 ([0080]). Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to continuing a normal processing step in the invention of Arvin by forming the next interconnection level as taught by Matsunaga above because Arvin is silent about the normal processing step, and Matsunaga teaches that it may prevent crack from being generated ([0002]). It would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to form a TaN layer as the barrier layer prior to depositing the aluminum conductive layer in the test structure, as taught by Matsunaga, in the invention of Arvin. Arvin fails to teach the claimed anti-reflective coating layer. Lien, also directed to fabricating a semiconductor integrated circuit, teaches that when patterning an reflective layer, such as an aluminum layer, by etching through a photoresist mask, the reflective layer often reflect light into regions of photoresist that are not intended to be irradiated during the forming of the photoresist mask, causing the resulting mask to be inaccurate, by causing, for example, notches in the mask or inaccurate line widths (Col. 1, Lines 13-26). In order to prevent such problem, Lien teaches to form an antireflective coating (ARC) layer on the reflective layer prior to applying the photoresist (Col. 1, Line 27-35). Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to form an ARC layer on the conductive layer prior to applying the photoresist in the invention of Arvin because Lien teaches that it would prevent undesired reflection that may cause inaccuracy in the mask. --Claims 2, 3, 4, 10, 13: Lien further teaches that forming the ARC layer may comprise forming a barrier layer, such as aluminum oxide, on the reflective layer, then forming an ARC layer on the barrier layer, wherein the barrier layer prevents the ARC layer from reacting with the reflective layer. Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to form the test structure 400 by i) forming a TaN barrier layer on the conductive interconnect 200, as taught by Matsunaga.ii) forming the aluminum conductive layer for the test structure 400iii) forming the aluminum oxide barrier layer, as taught by Lieniv) forming the ARC layer, as taught by Lien It is noted that one of skill in the art would be motivated to form the barrier layer in step (iii) of aluminum oxide because it is easier and cheaper to oxidize the existing aluminum layer then to deposit a new layer.--Claim 5, 21, 22, 23: Arvin further teaches that the patterning the test structure 400, i.e. step (h) above, may be performed by applying a lithography process then perform a wet chemical etch by using an acidic mixture of an oxidizer, such as hydrogen peroxide, and sulfuric acid ([0046]). Since acidic mixture of hydrogen peroxide and sulfuric acid is known in the art to etch polyimide and photoresist, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to form a recess on the insulating polymer layer 300 adjacent to the pattern of test pads and electrical connections. It is noted that the TaN layer reads on the first conductive layer, the aluminum layer reads on the second conductive layer, the aluminum oxide ARC layer reads on the ARC layer, the photoresist layer reads on the mask structure recited in claim 21.--Claim 8: Arvin further teaches that the electrical test for the integrated circuit, i.e. step (i) above, is performed by using probe pins on a portion of the test structure at a periphery of the circuit ([0048], Fig. 9).--Claim 9: It is noted that the probe pins contact the ARC layer at the surface of the test structure.--Claim 11: Lien further teaches that a barrier layer under an ARC layer may have a thickness 100-150 Å (Col. 3, Lines 1-5). Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to form the aluminum oxide barrier layer to a thickness about 100A in the invention of Arvin modified by Lien.--Claim 14: Since Lien teaches that aluminum oxide is used as an ARC layer, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, that the aluminum oxide ARC layer inhibits a reflection of light during the exposing the photoresist. --Claims 15, 16: Arvin further teaches that the patterning the test structure 400 may be performed by irradiating a laser through the hardmask 1000 ([0046], Fig. 8).--Claim 17: Arvin further teaches that the patterning the test structure 400 may be performed by RIE etching including Cl2 ([0046].
Claims 6-7 rejected under 35 U.S.C. 103 as being unpatentable over Arvin in view of Matsunaga and Lien as applied to claim 5 above, and further in view of Seddon (U.S. PGPub. No. 20190371670), hereinafter “Seddon”:--Claim 6: Arvin modified by Matsunaga and Lien teaches the invention as above. Arvin further teaches to continue normal processing step after removing the test structure. Seddon, also directed to making semiconductor devices (abstract), teaches that the semiconductor devices are formed within die in a semiconductor wafer (abstract, [0003]), wherein the wafer is mounted on a carrier tape, then cutting the wafer to separate the die ([0004-0012]), then picking the die from the carrier tape ([0027]). Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to continue the normal processing steps as taught by Seddon in the invention of Arvin because Arvin teaches to continue normal processing step after removing the test structure but is silent about the details, and Seddon teaches that those processes may be effective. --Claim 7: Fig. 9 shows that the step height at the edge of the test structure 400 is smaller than a step height formed when etching the patterned photoresist layer 500.
Claim 12 rejected under 35 U.S.C. 103 as being unpatentable over Arvin in view of Matsunaga and Lien as applied to claim 10 above, and further in view of Porter et al. (U.S. PGPub. No. 20220101992), hereinafter “Porter”:--Claim 12: Arvin modified by Matsunaga and Lien teaches the invention as above. Arvin further teaches that the test circuit may be used for testing during a C4 fabrication. Arvin fails to teach testing an LED circuitry. Porter, also directed to fabricating a semiconductor device, teaches that the semiconductor device may comprise a LED circuit in a flip-chip package ([0122, 0183]). Porter further teaches that test circuit pads may be fabricated for quality control during manufacturing ([0376]). It is noted that flip-chip package may use a C4 fabrication. Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to form the testing circuit over an LED circuit for the circuit testing, then remove the testing circuit and continuing normal fabrication in the invention of Arvin because Arvin teaches that the test circuit may be used for testing during a C4 fabrication, and Porter teaches that such testing may be necessary during fabrication of a flip-chip package comprising the LED circuitry.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS PHAM whose telephone number is (571) 270-7670 and fax number is (571) 270-8670. The examiner can normally be reached on MTWThF9to6 PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached on (571) 270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THOMAS T PHAM/Primary Examiner, Art Unit 1713
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