DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-10, 15 & 16-24 in the reply filed on 06/07/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 8-10, 15-17 & 19-24 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a0(2) as being anticipated by FAY et al. (KR 20220084107 – cited in the IDS submitted on March 05, 2026).
Regarding claim 1, FAY teaches a package-on-package 850, comprising:
at least two pre-packages (any two of the semiconductor dies 860A1-860D1 and polymer film 862, Fig. 8b), each pre-package of the at least two pre-packages including at least one chip (any of the semiconductor dies 860A1-860D1), a first redistribution layer 868 and first connectors 876, each chip having an active side and a passive side, each respective pre-package having an active side corresponding to the active side of each the at least one chip in the respective pre-package, and a passive side opposite to the active side of the respective pre-package (active surface/side of each pre-package faces passive surface/side of the other pre-package, see Fig. 8b) ; wherein:
the at least two pre-packages are stacked and interconnected (Fig. 8b), whereby the active side of one pre-package of two adjacent pre-packages faces the passive side of the other pre-package of the two adjacent pre-packages (Fig. 8b), and the first connectors 876 of the one pre-package of the two adjacent pre-packages are electrically connected with the first redistribution layer 868 of the other pre-package of the two adjacent pre-packages (Fig. 8b);
the first redistribution layer 868 in the respective pre-package is disposed on the active side of the respective pre-package (Fig. 8b), the first connectors 876 and the at least one chip in the respective pre- package are positioned on a same side of the first redistribution layer 868 (Fig. 8b); and
at least some of the first connectors 876 in the respective pre-package are located on at least one edge side of a respective chip of the at least one chip in the respective pre-package, and each of the at least some of first connectors 876 is electrically connected with the respective chip through the first redistribution layer 868 (see Fig. 8b).
Regarding claim 2, FAY teaches the package-on-package of claim 1, wherein each pre- package further comprises: a pre-encapsulation layer 862 that encapsulates the at least one chip and the first connectors 876, each first connector includes including a first conductive post; the first conductive post extends through the pre-encapsulation layer and is connected with the first redistribution layer of the each pre-package (Fig. 8b).
Regarding claim 8, FAY teaches the package-on-package of any one of claims claim 1, wherein the pre-package further comprises: bonding pads (Fig. 10b); the bonding pads are located on one side of the active surface of the chip, the bonding pads are distributed in an area of the chip close to the first connectors, and the bonding pads are electrically connected with the first connectors through the first redistribution layer (see planar view in Fig. 10b).
Regarding claim 9, FAY teaches the package-on-package of claim 1, wherein the at least one chip comprises at least one of a memory chip, a processor chip, a communication chip, a sense chip, and a power chip (Fig. 1-3 & 8b and associated text). Furthermore, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
Regarding claim 10, FAY teaches the package-on-package of claim 1, wherein the first connectors of adjacent pre-packages are disposed at corresponding positions (Fig. 8b).
Regarding claim 15, FAY teaches an electronic device, comprising: the package-on-package of claim 1 (Fig. 8b).
Regarding claim 16, FAY teaches a package, comprising:
stacked pre-packages (any two of the semiconductor dies 860A1-860D1 and polymer film 862, Fig. 8b), each pre-package of the stacked pre-packages having an active side and a passive side opposite to the active side, and including at least one chip, a first redistribution layer 868 and first connectors 876, each chip of the at least one chip having an active side corresponding to the active side of the respective pre-package, the first redistribution layer 868 is formed on the active side of the at least one chip and on the first connectors 876, the stacked pre-packages including a first pre-package (e.g. 860C1)and at least one second pre-package 860D1 stacked over the first pre-package 860C1, each of the first connectors 876 of a respective second pre-package having a first end connected to the first redistribution layer 868 of the respective second pre-package and a second end connected to the first redistribution layer of an adjacent pre-package disposed on the passive side of the respective second pre-package (Fig. 8b);
a second redistribution layer (note the second conductive trace 868) formed on the passive side of the first pre-package (e.g. bottom side of 860C1), each of the first connectors 876 of the first pre-package having a first end connected to the first redistribution layer of the first pre-package and a second end connected to the second redistribution layer (Fig. 8b);
second connectors 864 formed on a side of the second redistribution layer facing away from the stacked pre-packages (Fig. 8b); and
a substrate 852 on a side of the second connectors away from the second redistribution layer, the substrate 852 has a length greater than a length of each of the stacked pre-packages in a direction across a surface of the substrate facing the pre-packages (see Fig. 8b).
Regarding claim 17, FAY teaches the package of claim 16, wherein each pre-package further comprises: a pre- encapsulation layer 862, wherein the pre-encapsulation layer encapsulates the at least one chip and the first connectors of the each pre-package; wherein each of the first connectors of the each pre- package comprises a first conductive pillar; wherein the first conductive pillar penetrates the pre-encapsulation layer (Fig. 8b).
Regarding claim 19, FAY teaches the package of claim 17, further comprising: third connectors 856, wherein the third connectors are positioned on one side of the substrate 852 facing away from the second connectors, and are configured to connect to additional components (Fig. 8b).
Regarding claim 20, FAY teaches the package of claim 19, wherein each of the third connectors 856 includes at least one of a third conductive pillar and a solder ball (Fig. 8b).
Regarding claim 21, FAY teaches the package of claim 16, further comprising: an encapsulation layer 878 disposed on a side of the substrate facing the stacked pre-packages, wherein the encapsulation layer 878 encapsulates the stacked pre-packages (Fig. 8b).
Regarding claim 22, FAY teaches the package of claim 16, wherein the each pre-package further comprises bond pads on the active side of the at least one chip and electrically connected with the first connectors through the first redistribution layer (Fig. 10b).
Regarding claim 20, FAY teaches the package of claim 16, wherein the at least one chip comprises at least one of a memory chip, a computing chip, a communication chip, a sensor chip, and a power chip (Fig. 1-3 & 8b and respective text). Furthermore, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
Regarding claim 20, FAY teaches the package according to claim 16, wherein the first connectors of the stacked pre-packages are arranged at corresponding positions (Fig. 8b).
Allowable Subject Matter
Claims 3-7 & 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TIMOR KARIMY/Primary Examiner, Art Unit 2818
Prosecution Insights