DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I invention, claims 1-9, 15, and newly added claims 16-24, in the reply filed on May 26, 2026, is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 16-24 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hwang (U.S. Pub. 2023/0126686).
Regarding claims 16-24, Hwang [Figs.1-2] discloses a fan-out stack package, comprising:
stacked pre-packages [151,152], each pre-package of the stacked pre-packages having an active side [23F] and a passive side [23B] opposite to the passive side, and including at least one chip [21], a first redistribution layer [25/47/49] and first connectors [45/49], each chip of the at least one chip having an active side corresponding to the active side of the respective pre-package, the first redistribution layer is formed on the active side of the at least one chip and on the first connectors, the stacked pre-packages including a first pre-package [151] and at least one second pre-package [152] stacked over the first pre-package, each of the first connectors [45] of a respective second pre-package [152] having a first end connected to the first redistribution layer [25/47/49] of the respective second pre-package and a second end connected to the first redistribution layer of an adjacent pre-package disposed on the passive side [23B] of the respective second pre-package [Figs.1-2];
a second redistribution layer [61] formed on the passive side [23B] of the first pre-package [151], each of the first connectors [45] of the first pre-package having a first end connected to the first redistribution layer [25/47/49] of the first pre-package and a second end connected to the second redistribution layer [61]; and
second connectors [194] formed on a side of the second redistribution layer [61] facing away from the stacked pre-packages [Fig.1];
wherein the each pre-package further comprises: a pre-encapsulation layer [41/43/97], wherein the pre-encapsulation layer encapsulates the at least one chip [21] and the first connectors [45] of the each pre-package; wherein each of the first connectors of the each pre-package comprises a first conductive pillar [45];
wherein the first conductive pillar [45] penetrates the pre-encapsulation layer [41/43/97];
wherein:
the each of the first connectors of the each pre-package further comprises a metal bump [194];
the metal bump is electrically connected with the first conductive pillar [45] and is exposed outside a surface of the pre-encapsulation layer [Fig.2]; and
the metal bump is electrically connected with the first redistribution layer of the adjacent pre-package [Fig.1];
wherein the second connectors [194] are configured to connect with external components [142] [Bumps 194 are capable of the intended use];
wherein each of the second connectors [194] includes at least one of a second conductive pillar and a solder ball [194];
further comprising: an encapsulation layer [196] disposed on the active side of the first pre-package [151] facing the at least one second pre-package [152], wherein the encapsulation layer encapsulates the at least one second pre-package [Fig.1];
wherein the each pre-package further comprises bond pads [29] on the active side of the at least one chip and electrically connected with the first connectors [45] through the first redistribution layer [Fig.2] [Para.40];
wherein the at least one chip [21] comprises at least one of a memory chip, a computing chip, a communication chip, a sensor chip, and a power chip [Para.18];
wherein the first connectors [145] of two adjacent pre-packages are arranged at corresponding positions [Fig.1].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (U.S. Pub. 2023/0126686).
Regarding claim 1, Hwang [Figs.1,2,15] [Discussed above in the treatment of claims 16-24] discloses a fan-out stack package, comprising: at least two pre-packages; each pre-package including at least one chip, a first redistribution layer and first connectors, each chip of the at least one chip having an active side and a passive side, each respective pre-package of the at least two pre-packages having an active side corresponding to the active side of each the at least one chip in the respective pre-package, and a passive side opposite to the active side of the respective pre-package; wherein:
the at least two pre-packages are stacked and interconnected, the active side of one pre-package of any two adjacent pre-packages is opposite to the passive side of the other pre-package of the two adjacent pre-packages, and the first connectors of the one pre-package is electrically connected with the first redistribution layer of the other pre-package [Figs.1,2] [Discussed above in the treatment of claims 16-24];
wherein, in each pre-package of the at least two pre-packages, the first redistribution layer of the each pre-package is positioned on the active side of the at least one chip, and the first connectors and the at least one chip are positioned on a same side of the first redistribution layer; at least some of the first connectors [145] are positioned on at least one edge side of each of the at least one chip [21], and each of the first connectors is electrically connected with one or more of the at least one chip through the first redistribution layer [Figs.1,2] [Discussed above in the treatment of claims 16-24];
wherein the at least two pre-packages include a first pre-package and at least one second pre-package; the first pre-package is positioned at an outermost side of the fan-out stacked package for electrically connecting with external components [Figs.1,2] [Discussed above in the treatment of claims 16-24].
The above embodiment of Hwang [Figs.1,2] fails to explicitly disclose in a first preset direction perpendicular to a stacking direction, a length of the first pre-package is greater than that of the second pre-package. However, an embodiment of Hwang [Fig.15] discloses and makes obvious wherein in a first preset direction perpendicular to a stacking direction, a length of the first pre-package [188] is greater than that of the second pre-package [151/152].
It would have been obvious to provide wherein in a first preset direction perpendicular to a stacking direction, a length of the first pre-package is greater than that of the second pre-package, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 2-9 and 15, Hwang [Figs.1,2,15] discloses a fan-out stack package
wherein the each pre-package further comprises: a pre-encapsulation layer, wherein the pre-encapsulation layer encapsulates the at least one chip and the first connectors of the each pre-package; wherein each of the first connectors of the each pre-package comprises a first conductive pillar;
wherein the first conductive pillar penetrates the pre-encapsulation layer and is connected with a first redistribution layer of the pre-package [Figs.1,2,15] [Discussed above in the treatment of claims 16-24];
wherein the each of the first connectors of the each pre-package further comprises a metal bump;
the metal bump is electrically connected with the first conductive pillar and is exposed outside a surface of the pre-encapsulation layer; the metal bump is electrically connected with the first redistribution layer of the adjacent pre-package [Figs.1,2,15] [Discussed above in the treatment of claims 16-24];
further comprising a second redistribution layer and second connectors; wherein:
the second redistribution layer is disposed on the passive side of the first pre-package, the second connectors are located on a side of the second redistribution layer facing away from the first pre-package, the second redistribution layer connectors is electrically connected with the first connectors of the first pre-package and the second connectors, and the second connectors are configured to connect with external components [Figs.1,2,15] [Discussed above in the treatment of claims 16-24];
wherein each of the second connectors includes at least one of a second conductive pillar and a solder ball [Figs.1,2,15] [Discussed above in the treatment of claims 16-24];
further comprising: an encapsulation layer, wherein:
the encapsulation layer is disposed on one side of the first pre-package facing the at least one second pre-package, and the encapsulation layer encapsulates the at least one second pre-package [Figs.1,2,15] [Discussed above in the treatment of claims 16-24];
wherein the pre-package further comprises: bond pads;
the bond pads are located on the active side of the at least one chip, and the bond pads are electrically connected with the first connectors through the first redistribution layer [Figs.1,2,15] [Discussed above in the treatment of claims 16-24];
wherein the at least one chip comprises at least one of a memory chip, a computing chip, a communication chip, a sensor chip, and a power chip [Figs.1,2,15] [Discussed above in the treatment of claims 16-24];
wherein the first connectors of two adjacent pre-packages are arranged at corresponding positions [Figs.1,2,15] [Discussed above in the treatment of claims 16-24];
an electronic device, comprising: the fan-out stack package of claim 1 [Figs.1,15].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art is considered analogous art and discloses at least some of the claimed subject matter of the current invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BAC H AU whose telephone number is (571)272-8795. The examiner can normally be reached M-F 9:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BAC H AU/Primary Examiner, Art Unit 2898
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