CTNF 18/401,749 CTNF 79076 DETAILED ACTION Election/Restriction Applicant's election without traverse of Group I, claims 15 - 20, and newly added claims 21 - 34 is acknowledged. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 21 - 33 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Doyle et al. (2012/0235274) . With regard to claim 21, Doyle et al. disclose a method of forming an integrated device, comprising: forming a first wire level (a first wire level including wirings 414) over a substrate (402), the first wire level comprising a first contact wire (referred to as “W1” by examiner’s annotation shown in fig. 4 below; wherein the first contact wire W1 is portions of the wires 414, 420, and a conductive layer 1000) and a plurality of shield wires (referred to as “W2” by examiner’s annotation shown in fig. 4 below; wherein the shield wires are portions of the wires 414); forming a first etch stop layer (referred to as “450A1” by examiner’s annotation shown in fig. 4 below; wherein the first etch stop layer 450A1 is a portion of the etch stop layer 450) over the first wire level (the first wire level including the wiring stack 442); forming a second etch stop layer (referred to as “450A2” by examiner’s annotation shown in fig. 4 below; wherein the first etch stop layer 450A2 is a portion of the etch stop layer 450) over the first etch stop layer (450A1), the second etch stop layer (450A2) having a sidewall facing the first contact wire (referred to as “W1” by examiner’s annotation shown in fig. 4 below; wherein the first contact wire W1 is portions of the wires 414, 420, and a conductive layer 1000); performing an etching process to make a first opening (referred to as “OP1” by examiner’s annotation shown in fig. 4 below) extending through the first etch stop layer (450A1) to the first contact wire (W1) and a second opening (referred to as “OP2” by examiner’s annotation shown in fig. 4 below) extending through the second etch stop layer (450A2) to the first etch stop layer (450A1); and forming a metal-insulator-metal capacitor (a capacitor 434, having metal electrodes 997, 999 and an insulating layer 998, functions as a metal-insulator-metal capacitor) in the first opening (OP1) and the second opening (OP2), wherein the MIM capacitor (434) comprises a first lower surface (referred to as “434A1” by examiner’s annotation shown in fig. 4 below) on the first contact wire (W1) and a second lower surface (referred to as “434A2” by examiner’s annotation shown in fig. 4 below) on the first etch stop layer (450A1). PNG media_image1.png 675 747 media_image1.png Greyscale With regard to claim 22, Doyle et al. disclose the first lower surface (434A1) is spaced from the second lower surface (434A2) by the sidewall of the second etch stop layer (450A2). With regard to claim 23, Doyle et al. disclose forming a plurality of additional openings (referred to as “OP3” by examiner’s annotation shown in fig. 4 below; wherein the lower and upper spaces forming trenches functions as additional openings OP3) concurrently with forming the first opening (OP1) and the second opening (OP2), wherein the plurality of additional openings (OP3) are separated from the first wire level (the first wire level including wirings 414) by the first etch stop layer (450A1). PNG media_image2.png 672 748 media_image2.png Greyscale With regard to claim 24, Doyle et al. disclose the plurality of additional openings (OP3) are spaced from the first opening (OP1) by the sidewall of the second etch stop layer (450A2). With regard to claim 25, Doyle et al. disclose a bottom surface of the second etch stop layer (450A2) contacts a top surface of the first etch stop layer (450A1). With regard to claim 26, Doyle et al. disclose after the first wire level is formed, the plurality of shield wires (W2) are laterally spaced from the first contact wire in a first direction (X-direction), and wherein after the second etch stop layer (450A2) is formed, the second etch stop layer (450A2) extends away from the first contact wire (W1) in the first direction (X-direction). With regard to claim 27, Doyle et al. disclose forming the MIM capacitor (434) in the first opening (OP1) and the second opening (OP2) comprises forming a first metal layer (999) having the first lower surface (434A1) and the second lower surface (434A2), wherein the first lower surface (434A1) and the second lower surface (434A2) are at different heights relative to the first wire level (the first wire level including wirings 414). With regard to claim 28, Doyle et al. disclose a method of forming an integrated device, comprising: forming a first wire level (a first wire level including wirings 442) over a substrate (402), the first wire level comprising a first contact wire (referred to as “W1” by examiner’s annotation shown in fig. 4 below; wherein the first contact wire W1 is portions of the wires 414, 420, and a conductive layer 1000) and a plurality of shield wires (referred to as “W2” by examiner’s annotation shown in fig. 4 below; wherein the shield wires are portions of the wires 414); forming a first etch stop layer (referred to as “450A1” by examiner’s annotation shown in fig. 4 below; wherein the first etch stop layer 450A1 is a portion of the etch stop layer 450) over the first wire level (the first wire level including the wiring stack 442); forming an interlayer dielectric layer (428) over the first etch stop layer (450A1); etching a plurality of trenches (referred to as “T1”, and “T2” by examiner’s annotation shown in fig. 4 below) into the ILD layer (428), the plurality of trenches comprising a first trench (referred to as “T1” by examiner’s annotation shown in fig. 4 below) extending through the first etch stop layer (450A1), exposing the first contact wire (referred to as “W1” by examiner’s annotation shown in fig. 4 below; wherein the first contact wire W1 is portions of the wires 414, 420, and a conductive layer 1000), and a second trench (referred to as “T2” by examiner’s annotation shown in fig. 4 below) extending to a top surface of the first etch stop layer (450A1), where a bottom of the second trench (T2) is over a lower surface of the first etch stop layer (450A1); and forming a metal-insulator-metal capacitor (a capacitor 434, having metal electrodes 997, 999 and an insulating layer 998, functions as a metal-insulator-metal capacitor) in the first trench (T1) and the second trench (T2), wherein the MIM capacitor (434) comprises a first metal layer (a metal layer 997 or 999 functions as a first metal layer) contacting the first contact wire (W1) and the top surface of the first etch stop layer (450A1). PNG media_image3.png 659 735 media_image3.png Greyscale With regard to claim 29, Doyle et al. disclose forming a second etch stop layer (referred to as “450A2” by examiner’s annotation shown in fig. 4 below) over the first etch stop layer (450A1), wherein after the plurality of trenches (T1, T2) are etched, the second trench (T2) extends through the second etch stop layer (450A2) to the first etch stop layer (450A1). With regard to claim 30, Doyle et al. disclose a method of forming an integrated device, comprising: forming a first wire level (a first wire level including wirings 414) over a substrate (402), the first wire level comprising a first contact wire (referred to as “W1” by examiner’s annotation shown in fig. 4 below; wherein the first contact wire W1 is portions of the wires 414, 420, and a conductive layer 1000) and a plurality of shield wires (referred to as “W2” by examiner’s annotation shown in fig. 4 below; wherein the shield wires are portions of the wires 414); forming a first etch stop layer (referred to as “450A1” by examiner’s annotation shown in fig. 4 below; wherein the first etch stop layer 450A1 is a portion of the etch stop layer 450) over the first wire level (the first wire level including the wiring stack 414); forming an interlayer dielectric layer (428) over the first etch stop layer (450A1); etching a plurality of trenches (referred to as “T1”, and “T2” by examiner’s annotation shown in fig. 4 below) into the ILD layer (428), the plurality of trenches comprising a first trench (referred to as “T1” by examiner’s annotation shown in fig. 4 below) extending through the first etch stop layer (450A1), exposing the first contact wire (referred to as “W1” by examiner’s annotation shown in fig. 4 below; wherein the first contact wire W1 is portions of the wires 414, 420, and a conductive layer 1000), and a second trench (referred to as “T2” by examiner’s annotation shown in fig. 4 below) extending to a top surface of the first etch stop layer (450A1), where a bottom of the second trench (T2) is over a lower surface of the first etch stop layer (450A1); and forming a metal-insulator-metal capacitor (a capacitor 434, having metal electrodes 997, 999 and an insulating layer 998, functions as a metal-insulator-metal capacitor) in the first trench (T1) and the second trench (T2), wherein the MIM capacitor (434) comprises a first metal layer (a metal layer 997 or 999 functions as a first metal layer) contacting the first contact wire (W1) and the top surface of the first etch stop layer (450A1); the second etch stop layer (a left portion of the layer 450A2) is laterally spaced from the first trench by the ILD layer (a portion 428), and wherein the second etch stop layer (450A2) is exposed by the second trench (T2). PNG media_image4.png 680 760 media_image4.png Greyscale With regard to claim 31, Doyle et al. disclose the second trench (T2) is vertically separated from the plurality of shield wires (W2) by the first etch stop layer (450A1). With regard to claim 32, Doyle et al. disclose forming a second wire layer (404, 408) before forming the first wire level (the first wire level including wirings 442), wherein after the MIM capacitor (434) is formed, the second wire layer (404, 408) is spaced from the MIM capacitor (434) by the plurality of shield wires (W2) in the first wire level. PNG media_image3.png 659 735 media_image3.png Greyscale With regard to claim 33, Doyle et al. disclose the first trench (T1) has a greater depth than the second trench (T2) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 15, 17, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Doyle et al. (2012/0235274) in view of PARK et al. (20240275387) . With regard to claim 15, Doyle et al. disclose a method of forming an integrated device (for example, see fig. 4), comprising: forming a first wire level (a first wire level including a wiring stack 442) over a substrate (402), the first wire level comprising a first contact wire (referred to as “W1” by examiner’s annotation shown in fig. 4 below; wherein the first contact wire W1 is portions of the wires 414, 420, and a conductive layer 1000) and a plurality of shield wires (referred to as “W2” by examiner’s annotation shown in fig. 4 below; wherein the shield wires are portions of the wires 414); forming a first etch stop layer (referred to as “450A1” by examiner’s annotation shown in fig. 4 below; wherein the first etch stop layer 450A1 is a portion of the etch stop layer 450) over the first wire level (the first wire level including the wiring stack 442); forming a second etch stop layer (referred to as “450A2” by examiner’s annotation shown in fig. 4 below; wherein the first etch stop layer 450A2 is a portion of the etch stop layer 450) over the first etch stop layer (450A1), the second etch stop layer (450A2) having an opening (referred to as “OP” by examiner’s annotation shown in fig. 4 below) over the first contact wire (W1); forming an interlayer dielectric layer (428) over the first etch stop layer (450A1) and the second etch stop layer (450A2); etching a plurality of trenches (referred to as “T1”, and “T2” by examiner’s annotation shown in fig. 4 below) into the ILD layer (428), the plurality of trenches comprising a first trench (referred to as “T1” by examiner’s annotation shown in fig. 4 below) extending through the opening (OP) and into the first etch stop layer (450A1), exposing the first contact wire (referred to as “W1” by examiner’s annotation shown in fig. 4 below; wherein the first contact wire W1 is portions of the wires 414, 420, and a conductive layer 1000), and a second trench (referred to as “W2” by examiner’s annotation shown in fig. 4 below) extending into the second etch stop layer (450A2) over the plurality of shield wires (W2), where a bottom of the second trench (T2) is over a lower surface of the first etch stop layer (450A1); and forming a metal-insulator-metal capacitor (a capacitor 434, having metal electrodes 997, 999 and an insulating layer 998, functions as a metal-insulator-metal capacitor) in the first trench (T1) and the second trench (T2), wherein the MIM capacitor (434) comprises a protrusion (referred to as “P1” by examiner’s annotation shown in fig. 4 below) in the first trench (T1) and a second protrusion (referred to as “P2” by examiner’s annotation shown in fig. 4 below) in the second trench (T2). PNG media_image3.png 659 735 media_image3.png Greyscale Doyle et al. do not clearly disclose forming the metal-insulator-metal capacitor over an upper surface of the ILD layer. However, PARK et al. discloses a metal-insulator-metal capacitor (200) over an upper surface of the ILD layer (130). PNG media_image5.png 537 662 media_image5.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Doyle et al.’s device to forming the metal-insulator-metal capacitor over an upper surface of the ILD layer as taught by Park et al.in order to a high capacitance efficiency of the capacitor for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. With regard to claim 17, Doyle et al. disclose etching of the plurality of trenches (T1, T2) is inherently performed using a single etching process. (because the trenches T1, T2, are formed in the same capacitor trench having trenches T1, T2). With regard to claim 19, Doyle et al. disclose the first trench (T1) has a first depth measured from an upper surface (a top surface) of the ILD layer (428) and the second trench (T2) has a second depth measured from the upper surface (the top surface) of the ILD layer (428), and wherein the first depth is greater than the second depth (because a bottom surface of the first trench T1 is lower than a bottom surface of the second trench T2). . With regard to claim 20, Doyle et al. disclose the second trench (T2) extends through the second etch stop layer (450A2), but is separated from the shielding wires (W2) by the first etch stop layer (450A1) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 6. Claim s 16, 18, 34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 16, 18, 34 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as forming a first conformal metal layer over the ILD layer and in the first trench and the second trench; forming a first conformal intermetal dielectric layer over the first conformal metal layer and in the first trench and the second trench; forming a second conformal metal layer over the first conformal intermetal dielectric layer, filling the first trench and the second trench; and etching the first conformal metal layer, the first conformal intermetal dielectric layer, and the second conformal metal layer to delineate a bottom metal layer, an intermetal dielectric, and a top metal layer as recited in claim 16, the single etching process has first etch rate when etching through the ILD layer, and a second etch rate when etching through the first etch stop layer and second etch stop layer, and the first etch rate is greater than the second etch rate as recited in claim 18, the plurality of trenches further comprises a third trench spaced from the first trench by the second trench and a fourth trench spaced from the second trench by the third trench, wherein the third trench extends to the top surface of the first etch stop layer and the fourth trench extends through the first etch stop layer to a second contact wire within the first wire level as recited in claim 34. Conclusion 7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TAN N TRAN/ Primary Examiner, Art Unit 2812 Application/Control Number: 18/401,749 Page 2 Art Unit: 2812 Application/Control Number: 18/401,749 Page 3 Art Unit: 2812 Application/Control Number: 18/401,749 Page 4 Art Unit: 2812 Application/Control Number: 18/401,749 Page 5 Art Unit: 2812 Application/Control Number: 18/401,749 Page 6 Art Unit: 2812 Application/Control Number: 18/401,749 Page 7 Art Unit: 2812 Application/Control Number: 18/401,749 Page 8 Art Unit: 2812 Application/Control Number: 18/401,749 Page 9 Art Unit: 2812 Application/Control Number: 18/401,749 Page 10 Art Unit: 2812 Application/Control Number: 18/401,749 Page 11 Art Unit: 2812 Application/Control Number: 18/401,749 Page 12 Art Unit: 2812 Application/Control Number: 18/401,749 Page 13 Art Unit: 2812 Application/Control Number: 18/401,749 Page 14 Art Unit: 2812
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