DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of 17-21 & 22-36 in the reply filed on 04/01/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 17-20, 22 & 24-32 & 34-36 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by OGUZ et al. (US Pub. 2023/0411443).
Regarding claim 17, OGUZ teaches a method of forming an integrated circuit (IC) device, the method comprising:
providing a semiconductor substrate having a first contact region and a second contact region (Para [0044-0046] and see Fig. 2 below);
forming a metal interconnect structure comprising a plurality of metallization layers over the semiconductor substrate (Para [0044-0046 & Fig. 2);
forming a first dielectric layer 222 over the metal interconnect structure (Fig. 2);
forming a trench 130/230 extending into the first dielectric layer 122/222 (Fig.1 - Fig. 2) ;
forming a first electrode metal layer 231 over the first dielectric layer and within the trench (Fig. 2);
forming a first mask 512 and etching to selectively remove the first electrode metal layer 231/531 from the first contact region (Fig. 2 & Fig. 5B-5C, OGUZ also discusses the use of mask in patterning and selective removal of layers in Para [0160-0161]);
forming a capacitor dielectric layer 235/535 and a second electrode metal layer 232/532 over the first electrode metal layer 231/531 (Fig. 2 and Fig. 5D-5E);
forming a second mask 517 and etching to selectively remove the second electrode metal layer 535 from the second contact region (Fig. 5F-5G, OGUZ also discusses the use of mask in patterning and selective removal of layers in Para [0160-0161]));
forming a second dielectric layer 223/522 above the second electrode metal layer 232/532;
etching holes, wherein the holes comprise a first hole in the first contact region and a second hole in the second contact region, wherein the first hole extends through the second dielectric layer 223/522, the second electrode metal layer 232/532, and the first dielectric layer 222/521, and the second hole extends through the second dielectric layer 223/522, the first electrode metal layer 231/531, and the first dielectric layer 222/522 (see Fig. 5H-Fig. 5I); and
filling the holes with conductive material to form vias including a first via in the first hole and a second via in the second hole, wherein the first via contacts the second electrode metal layer 232/532 and the second via contacts the first electrode metal 231/531 layer (Fig. 2 & Fig. 5H-Fig. 5I and associated texts).
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Regarding claim 18, OGUZ teaches the method of claim 17, wherein etching to selectively remove the first electrode metal layer 231/531 from the first contact region leaves the first electrode metal layer surrounding the first contact region (see Fig. 2 above & Fig. 5B-Fig. 5C).
Regarding claim 19, OGUZ teaches the method of claim 17, wherein etching to selectively remove the second electrode metal layer 232/532 from the second contact region is an etch process that stops on the capacitor dielectric layer (Fig. 5F-Fig. 5G).
Regarding claim 20, OGUZ teaches the method of claim 17, wherein forming the capacitor dielectric layer 235/535 comprises a deposition process that causes the capacitor dielectric layer to be thinner within the trench than outside the trench (it is understood that the capacitor components inside the trench is thinner than the components outside the trench, Fig. 2).
Regarding claim 22, OGUZ teaches a method of forming an integrated circuit (IC) device, the method comprising:
receiving a semiconductor substrate having a first region and a second region (see Fig. 2 above and Para {0044-0046]);
forming a plurality of metallization layers interleaved with via layers over the semiconductor substrate, wherein an uppermost of the plurality of metallization layers includes a first wire 143 and a second wire 143 (Fig. 2 above and Para [0044-0046]);
depositing a first dielectric structure 122 over the uppermost of the plurality of metallization layers (Fig. 2 and Para [0044-0046]);
etching one or more trenches 530 in the first dielectric structure 521 (Fig. 5A);
depositing a first electrode metal layer 531 over the first dielectric structure 521 and within the one or more trenches 530 (Fig. 5B);
selectively removing the first electrode metal layer 531 from the first region (Fig. 2 & Fig. 5B-5C);
depositing a first dielectric layer 535 over the first electrode metal layer 531 (Fig. 5D);
depositing a second electrode metal layer 532 over the first dielectric layer 535 (Fig. 5E);
selectively removing the second electrode metal layer 532 from the second region (Fig. 2 & Fig. 5F-5G);
depositing a second dielectric structure 522 above the second electrode metal layer 532 (Fig. 5H);
etching holes including one or more first holes in the first region and one or more second holes in the second region (Fig. 5I), wherein:
the one or more first holes (note first hole housing via 542) extend through the second dielectric structure 522, the second electrode metal layer 532, and the first dielectric structure 521 (Fig. 5I); and
the one or more second holes (note second holes housing via 542) extend through the second dielectric structure 522, the first electrode metal layer 531, and the first dielectric structure 521 (Fig. 5I); and
depositing conductive material 542, wherein the conductive material fills the one or more first holes and the one or more second holes to form vias including one or more first vias corresponding to the first holes and one or more second vias corresponding to the one or more second holes, wherein the one or more first vias contact the second electrode metal layer 532 and the first wire 543, and the one or more second vias contact the first electrode metal layer 531 and the second wire 543 (Fig. 5I & Fig. 2).
Regarding claim 24, OGUZ teaches the method of claim 22, wherein the one or more trenches comprise at least three trenches between the first region and the second region (Fig. 2, OGUZ teaches in Para [0058] where multiple trenches, including three trenches, can be between the first and second regions).
Regarding claim 25, OGUZ teaches the method of claim 22, wherein the one or more trenches comprise at least one trenches on a first side of the first region and second trench on an opposite side of the first region (Fig. 2).
Regarding claim 26, OGUZ teaches the method of claim 22, wherein the one or more first vias comprise a plurality of vias (Fig. 2).
Regarding claim 27, OGUZ teaches the method of claim 22, wherein depositing conductive material forms a layer of conductive material above the second dielectric structure 522, and the method further comprises patterning the conductive material to form contact pads 541 (Fig. 5I).
Regarding claim 28, OGUZ teaches the method of claim 22, wherein: a bottommost layer (e.g. 221) of the first dielectric structure is an etch stop layer in direct contact with the uppermost of the plurality of metallization layers; and the one or more trenches extend to the etch stop layer 221 (Fig. 2).
Regarding claim 29, OGUZ teaches a method, comprising: forming a metal interconnect structure (e.g. note 243 on the left and right in Fig. 2) over a substrate (Para [0044-0046]);
forming a passivation stack (222 or 222 & 223) over the metal interconnect structure (Fig. 2);
forming a deep trench capacitor 220 in the passivation stack, wherein the deep trench capacitor comprises a first electrode plate 231 and a second electrode plate 232 (Fig. 2);
forming first and second vias 242 through the passivation stack (Fig. 2);
wherein the first and second vias 242 are electrically isolated from one another (Fig. 2);
wherein the first via (242 on the right) contacts the first electrode plate 231 and a first wire (243 on the right) within the metal interconnect structure (Fig. 2); and
the second via (242 on the left) contacts the second electrode plate 231and a second wire (243 on the left) within the metal interconnect structure (Fig. 2, also see Fig. 4 & Fig. 9C) .
Regarding claim 30, OGUZ teaches the method of claim 29, wherein: the deep trench capacitor further comprises a third electrode plate; the second electrode plate is between the first and third electrode plates and is separated from the first and third electrode plates by high-k dielectric; and first via contacts the third electrode plate (Para [0092] where OGUZ teaches adding additional electrodes and intervening dielectric (e.g. high-K, Para [0122]) to increase total capacitance).
Regarding claim 31, OGUZ teaches the method of claim 29, further comprising forming a first contact and a second contact (note contacts 241 on the left and right), wherein the first contact is electrically coupled to the first via and the second contact is electrically coupled to the second via (Fig. 2).
Regarding claim 32, OGUZ teaches the method of claim 31, further comprising coupling the first contact and the second contact to respective first and second terminals of a power supply (Fig. 2, also see Para [0118]). Furthermore, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
Regarding claim 34, OGUZ teaches the method of claim 29, wherein the deep trench capacitor comprises trench structures on opposite sides of the first via (Fig. 2).
Regarding claim 35, OGUZ teaches the method of claim 29, wherein the deep trench capacitor extends through the passivation stack to an etch stop layer at a base of the passivation stack (Para [0157]).
Regarding claim 36, OGUZ teaches the method of claim 29, further comprising forming first and second contacts 241 over the passivation stack, wherein the first via 242 couples the first contact to the first wire 243 and the second contact 241 couples the second contact to the second wire 243 (see Fig. 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 33 is rejected under 35 U.S.C. 103 as being unpatentable over OGUZ as applied to claim 29 above, and further in view of LI et al. (US Pub. 2022/0123101).
Regarding claim 33, OGUZ is silent on the method of claim 29, wherein the passivation stack comprises a barrier layer, and the deep trench capacitor extends into the barrier layer. However, LI discloses wherein a passivation stack 270 comprises a barrier layer (lower portion of 270 under etch stop layer 282), and the deep trench capacitor extends into the barrier layer (see Fig. 2B & 4F). This has the advantage of employing multiple metallization/dielectric (e.g. including a barrier) layer to increase capacitance while maintaining mechanical stability and the overall structure compact. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of OGUZ with the barrier layer, as taught by LI, so as to increase capacitance while keeping the device structure compact.
Allowable Subject Matter
Claims 21 & 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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