Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The phrase “outside” is unclear in view of the specification.
Claim 1 recites: a through substrate via (TSV) extending vertically through the second substrate laterally outside of the plurality of pixel support devices and directly below the pixel array.
Claim 11 recites: and a through substrate via (TSV) extending vertically through the second substrate directly below the pixel array and laterally outside of the plurality of pixel support devices.
Claim 17 recites bonding the first IC tier to the second IC tier so that one or more regions of the second substrate are laterally outside of the plurality of pixel support devices and vertically below the pixel array
Claims 1,11 and 17 are unclear due to the word outside. All the embodiments of applicant’s disclosure have the TSV between pixel support devices e.g. figure 1 item 120 is between items 116 in the plane. Further, figure 1 description paragraph 28 states: A through-substrate-via (TSV) 120 extends through the second substrate 104b directly below the pixel array 108 and within the one or more regions that are laterally outside of the plurality of pixel support devices 116. The TSV 120 electrically connects the second plurality of interconnects 114b to the third plurality of interconnects 114c. In some embodiments, the TSV 120 may extend through the second substrate 104b directly below the one or more dummy pixel regions 108d. Because the one or more regions are located below the pixel array 108, the TSV 120 is able to provide for a relatively short electrical connection between the plurality of logic devices 118 and either plurality of image sensing elements 106 and/or the plurality of pixel support devices 116. The relatively short electrical connection reduces a parasitic resistance of the multi-dimensional image sensor IC structure 100 and improves a performance of the multi-dimensional image sensor IC structure 100.
Figure 1 as a whole shows item 120 is interior to items 116. This is repeated in Figure 18 and paragraph 78 with item 120 depicted as interior to two 116 or between them but described as outside.
The term outside means:
a. the outer side, surface, or part; exterior.
b. the space without or beyond an enclosure, institution, boundary, etc..
c. a position away or farther away from the inside or center.
The best the examiner can determine the most fitting definition would be definition c.
However, figure 1 shows it oriented in the center of the devices.
Therefore, the examiner will interpret outside to mean only “away”.
b. As to claim 8, Claim 8 is unclear since it recites one or more additional through substrate vias (TSVs) extending vertically through the second substrate laterally outside of the plurality of pixel support devices and directly below the pixel array, wherein the TSV and the one or more additional TSVs are arranged between adjacent ones of the plurality of active pixel regions along a cross-sectional view.
Applicant has not set for a structure between the active pixels the active pixels are either depicted directly adjacent to one another thus there is nothing between the active pixel regions or with a dummy pixel separating them (see all cross-sectional views of applicant). Thus, applicant has not adequately structurally related the “between” to the dummy pixel regions.
c. As to claim 14 recites wherein the TSV is part of a TSV array arranged between sides of the plurality of active pixel regions facing one another.
Recitation active pixel regions facing one another lacks antecedent basis.
d. As to claim 18 recitations of a front side and back side is unclear since they are arbitrary.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 6 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Park (20230076351) cited on ids with Miyake 20240072093 as evidence.
a. As to claim 1 the claim makes reference to “dummy pixel region” Miyake teaches dummy structure maybe same structure as an active pixel simply not outputting a signal (item 310a paragraph 103 and figure 8 which has interconnect structures associated with the dummy pixels). Thus, the phrase dummy pixel region without additional structure is interpreted as an intended or desired usage of element. To seek consistency among the claims it is noted claims 4 and 10 further limit the structure of a dummy pixel by not having interconnects or transfer gates. Claim 4 and 10 depend from claim 1 thus the term dummy must be broader, thus the office will consider “dummy pixel regions” without further structure as an intended usage or merely a label.
Park teaches A multi-dimensional image sensor integrated chip (IC) structure, comprising: a plurality of image sensing elements disposed within a plurality of pixel regions arranged in a pixel array of a first integrated chip (IC) tier(items PD figure 5), wherein the plurality of pixel regions comprise a plurality of active pixel regions and one or more dummy pixel regions any of the PD could be acting as a dummy (also see paragraph 57:
The sensor array region SAR includes a light receiving region APS and a light blocking region OB. Active pixel that receive light and generate active signals are arranged in the light receiving region APS. Optical black pixels that generate optical black signals by blocking light are arranged in the light blocking region OB. The light blocking region OB is formed, for example, along the periphery of the light receiving region APS, but embodiments are not limited thereto. In some embodiments, dummy pixels are formed in the light receiving region APS adjacent to the light blocking region OB. The dummy pixels are pixels that do not generate an active signal. Thus, the dummies would be between the active ABS and Active OB.
a plurality of pixel support devices disposed on a second substrate within a second IC tier that is bonded to the first IC tier(item 240 and item 200 figure 4); a plurality of logic devices disposed within a third IC tier that is bonded to the second IC tier (figure 4 and 5 item 300 item 30 Park teaches attached the phrase “bonded” is product by process and does not structural differentiate) ; and a through substrate via (TSV) extending vertically through the second substrate laterally outside of the plurality of pixel support devices and directly below the pixel array (TSV 1 is away from the TR1 due to 243 in figure 5 TSVs are below the active pixels.).
b. AS to claim 2, Park teaches : a plurality of transfer gates arranged on a first substrate of the first IC tier and respectively disposed within one of the plurality of active pixel regions (items 130 figure 5), wherein TSV1 is laterally between a first transfer gate and a second transfer gate of the plurality of transfer gates, as viewed in a cross-sectional view (it is between some arbitrary 130s the claim does not require nearest neighbor).
c. As to claim 3, Park teaches further comprising: one or more dummy image sensing elements disposed within the one or more dummy pixel regions, wherein the one or more dummy image sensing elements are electrically isolated from the plurality of pixel support devices (paragraph 57 element 120 isolates pixels from one another).
d. As to claim 6, Park teaches one or more peripheral TSV vertically extending through the second substrate at one or more locations that are laterally outside of the pixel array (figure 5 item TSV2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5 and 7, and 10-19, is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view Oh 20180197904 evidenced by Miyake.
a. AS to claims 4 and 10, Park teaches wherein the first IC tier comprises a first interconnect structure disposed on a first substrate (item 140), appears to teach figure 5 that the edge most pixel in OB towards PR that the first interconnect structure being devoid of interconnects directly below the one or more dummy pixel regions thus for the edge pixel it would read on the claim.
However, assuming arguendo, it cannot be interpreted in that manner.
Oh, teaches wherein the first IC tier comprises a first interconnect structure disposed on a first substrate, the first interconnect structure being devoid of interconnects directly below the one or more dummy pixel regions (items 152/160 figure 11 present in PR and OB regions but not present in the DR region). Oh, further teaches the dummy region is also devoid of transfer gates TG missing from FR region.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide no interconnect structure and transfer gates under dummy pixels to ensure electrical isolation and no active signal is sent (paragraph 57 of Park).
b. As to claims 5 and 7, Park can be interpreted to herein the one or more dummy pixel regions are laterally surrounded by the plurality of active pixel regions along a first direction and along a second direction that is perpendicular to the first direction as viewed in a top-view of the pixel array since “dummy pixel region” is an intended use base on figure 4 any interior pixel can be interpreted as a dummy and thus surrounded by active pixels.
Park teaches 120, an isolation, are electrically conductive (paragraph 113) or wherein the plurality of active pixel regions has a first width and the one or more dummy pixel regions have a second width measured along a cross-sectional view, the first width being different than the second width.
Further Oh explicitly teaches wherein the one or more dummy pixel regions are laterally surrounded by the plurality of active pixel regions along a first direction and along a second direction that is perpendicular to the first direction as viewed in a top-view of the pixel array (figure 9 DR1E DR2E paragraphs 75-78). Oh, also teaches that wherein the plurality of active pixel regions has a first width and the one or more dummy pixel regions have a second width measured along a cross-sectional view, the first width being different than the second width (DR1 DR2 vs other pixels figure 9).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the Dummy region with the associated widths with the associated electrical contact to provide stable electrical connection for the isolation even if pixels are misaligned paragraph 77 of Oh:
Therefore, even if misalignment occurs due to a tolerance in a process of forming the pixel separation contact 140E, a stable electrical connection between the pixel separation contacts 140E and the pair of dummy pixel regions DR1E and DR2E may still be formed.
c. As to claim 11, the claim makes reference to “dummy pixel region” Miyake teaches dummy structure maybe same structure as an active pixel simply not outputting a signal (item 310a paragraph 103 and figure 8 which has interconnect structures associated with the dummy pixels). Thus, the phrase dummy pixel region without additional structure is interpreted as an intended or desired usage of element. To seek consistency among the claims it is noted claims 4 and 10 further limit the structure of a dummy pixel by not having interconnects or transfer gates. Claim 4 and 10 depend from claim 1 thus the term dummy must be broader, thus the office will consider “dummy pixel regions” without further structure as an intended usage or merely a label.
Park An image sensor integrated chip (IC) structure, comprising: a pixel array comprising a plurality of image sensing elements disposed within a plurality of pixel regions of a first substrate( figure 4 and 5 item 100), wherein the plurality of pixel regions include a plurality of active pixel regions laterally surrounding one or more dummy pixel regions (dummy is relative any active pixel can be considered a dummy also paragraph 57 explicitly discloses since the Dummies would be between APS and OB both are active) ; a plurality of pixel support devices disposed within a second substrate stacked on the first substrate and coupled to a second interconnect structure on the second substrate TR connected by 240 and 140), wherein the plurality of active pixel regions respectively comprise one or more of the plurality of image sensing elements that are electrically coupled to the plurality of pixel support devices (figure 5); a plurality of logic devices disposed on a third substrate stacked on the second substrate and coupled to a third interconnect structure on the third substrate (figure 5TR2 connected via 344 and 343 and TSVs see figure 4 for “logic recitation); and a through substrate via (TSV) extending vertically through the second substrate directly below the pixel array and laterally outside of the plurality of pixel support devices (TSV1 the term outside is not clear it is away from TR1 thus outside).
If the term “lateral must mean all sides Park does not appear all “lateral sides.”
Park teaches 120 isolations are electrically conductive (paragraph 113)
Oh, teaches wherein the one or more dummy pixel regions are laterally surrounded by the plurality of active pixel regions along a first direction and along a second direction that is perpendicular to the first direction as viewed in a top-view of the pixel array (figure 9 DR1E DR2E paragraphs 75-78).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the Dummy region with the associated electrical contact to provide stable electrical connection for the isolation even if pixels are misaligned paragraph 77 of Oh.
d. As to claims 12 and 13, whether an element is active or passive a matter of intended usage applicant provides no differentiating structure that defines a dummy vs active thus one can arbitrary define either of :
wherein the plurality of pixel support devices is arranged directly below the plurality of active pixel regions and the TSV is arranged directly below the one or more dummy pixel regions
wherein the plurality of pixel support devices is arranged directly below the one or more dummy pixel regions and the TSV is arranged directly below the plurality of active pixel regions
Thus, since pixels with Transistors can be defined as either active or dummy and the one with TSV can be defined as either dummies or passive (figure 5 of Park).
e. As to claim 14, The two TSVs of Park region APS cand be considered an array figure 5 is between OB active pixels or other APS active pixels not depicted but in 100 on sides of pixel array 1. Thus, the TSVs are arranged between sides of the plurality of active pixel regions facing one another.
f. As to claim 15, Park teaches further comprising: one or more dummy image sensing elements disposed within the one or more dummy pixel regions, wherein the one or more dummy image sensing elements are electrically isolated from the plurality of pixel support devices (paragraph 57 element 120 isolates pixels from one another).
g. As to claim 16, Park teaches wherein the TSV electrically connects the second interconnect structure to the third interconnect structure (TSV connects LM to the 340s figure 5).
h. As to claim 17, the claim makes reference to “dummy pixel region” Miyake teaches dummy structure maybe same structure as an active pixel simply not outputting a signal (item 310a paragraph 103 and figure 8 which has interconnect structures associated with the dummy pixels). Thus, the phrase dummy pixel region without additional structure is interpreted as an intended or desired usage of element. To seek consistency among the claims it is noted claims 4 and 10 further limit the structure of a dummy pixel by not having interconnects or transfer gates. Claim 4 and 10 depend from claim 1 thus the term dummy must be broader, thus the office will consider “dummy pixel regions” without further structure as an intended usage or merely a label.
Park teaches A method of forming an image sensor integrated chip (IC) structure, comprising: forming a first integrated chip (IC) tier comprising a plurality of image sensing elements within a pixel array in a first substrate (figures 4 and 5 item 100), the pixel array including a plurality of active pixel regions (APS and OB figure 5) surrounding one or more dummy pixel regions (dummy is relative any active pixel can be considered a dummy also paragraph 57 explicitly discloses since the Dummies would be between APS and OB both are active); forming a second IC tier comprising a plurality of pixel support devices on a second substrate (figures 4 and 5 item 200); bonding the first IC tier to the second IC tier (Paragraph 84 140 is bonded to 240) so that one or more regions of the second substrate are laterally outside of the plurality of pixel support devices and vertically below the pixel array (TSV1 the term outside is not clear it is away from TR1 thus outside); forming a through substrate via (TSV) to extend through the one or more regions of the second substrate (TSV1s) ; forming a third IC tier comprising a plurality of logic devices on a third substrate (item 300 figures 4 and 5); and attached the third IC tier to the second IC tier (paragraph 93).
Park does not explicitly teach “bonding” of the second to the third tier.
However, bonding was known to attach paragraph 84 Park.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to have attached via bonding the 2nd tier to the 3rd tier to ensure good adhesion and to use conventional method to obtain expected results.
If the term “lateral” must mean all sides - Park does not appear all “lateral sides.”
Park teaches 120 isolations are electrically conductive (paragraph 113)
Oh, teaches wherein the one or more dummy pixel regions are laterally surrounded by the plurality of active pixel regions along a first direction and along a second direction that is perpendicular to the first direction as viewed in a top-view of the pixel array (figure 9 DR1E DR2E paragraphs 75-78).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the Dummy region with the associated electrical contact to provide stable electrical connection for the isolation even if pixels are misaligned paragraph 77 of Oh.
i. As to claim 18 if the interconnect is front and the substrate is back Park teaches bonding a front-side of the first substrate to a front-side of the second substrate; and bonding a front-side of the third substrate to a back-side of the second substrate since 140 is bonded to 240 and the substrate 210 is bonded to the insulation 340.
j. As to claim 19, Park does not explicitly teach etching the back-side of the second substrate to form a TSV opening extending through the second substrate; and forming the TSV within the TSV opening.
However, to form vias it was known to form by etching either the back to form the via hole and fill.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to etch from the back side fill and then bond the tier 2 to tier 3.
One would have been so motivated to use known techniques to provide the expected and known outcome of functional TSVs
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Iwata (20240355856) evidenced by Miyake.
a. As to claims 8-9, since Dummy pixel region without further structure is arbitrary Parks TSV1 can be interpreted as one or more additional through substrate vias (TSVs) extending vertically through the second substrate laterally outside of the plurality of pixel support devices and directly below the pixel array, wherein the TSV and the one or more additional TSVs are arranged between adjacent ones of the plurality of active pixel regions along a cross-sectional view since the regions in figure 5 for which the TSV1 are in can be interpreted as dummy pixel regions.
Further Itawa teaches paragraph 268: Pixels disposed in the region overlapping the TSV wires in a planar view are not limited to effective pixels that output signals based on photoelectric conversion. For example, the pixel may be an optical black pixel (OB pixel) with its light incidence surface side covered by a light shielding film in such a manner that light does not enter, and a dummy pixel not being connected with an output line and not outputting signals. The dummy pixel is a pixel disposed between the effective pixel and the dummy pixel to prevent oblique light incidence to the OB pixel, for example. Because small influence is exerted on image quality even if such a pixel is influenced by a voltage input or output via the TSV wires, arranging dummy pixels in a region overlapping the TSV wires in a planar view results in efficient utilization of the area.
Thus, it would be obvious to provide Dummy pixels between effective pixels to prevent oblique light incidence on them and providing the TSV in the Dummy pixels for efficient utilization of area as suggested by Itawa paragraph 268.
Claim(s) 12 13 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view Oh 20180197904 in further view of Iwata (20240355856) evidenced by Miyake.
a. As to claims 12-13 and 20 Since Dummy pixel region without further structure is arbitrary Parks TSV1 can be interpreted as one or more additional through substrate vias (TSVs) extending vertically through the second substrate laterally outside of the plurality of pixel support devices and directly below the pixel array, wherein the TSV and the one or more additional TSVs are arranged between adjacent ones of the plurality of active pixel regions along a cross-sectional view since the regions in figure 5 for which the TSV1 are in can be interpreted as dummy pixel regions.
Further Itawa teaches paragraph 268: Pixels disposed in the region overlapping the TSV wires in a planar view are not limited to effective pixels that output signals based on photoelectric conversion. For example, the pixel may be an optical black pixel (OB pixel) with its light incidence surface side covered by a light shielding film in such a manner that light does not enter, and a dummy pixel not being connected with an output line and not outputting signals. The dummy pixel is a pixel disposed between the effective pixel and the dummy pixel to prevent oblique light incidence to the OB pixel, for example. Because small influence is exerted on image quality even if such a pixel is influenced by a voltage input or output via the TSV wires, arranging dummy pixels in a region overlapping the TSV wires in a planar view results in efficient utilization of the area.
Thus, it would be obvious to provide Dummy pixels between effective pixels to prevent oblique light incidence on them and providing the TSV in the Dummy pixels for efficient utilization of area as suggested by Itawa paragraph 268.
Thus it would be obvious to provide Dummy pixels between effective pixels to prevent oblique light incidence on them and providing the TSV in the active pixels for efficient utilization of area as suggested by Itawa paragraph 268.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896