DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 & 21-30 in the reply filed on 04/01/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-6, 8, 10, 21, 25, 27 & 28-30 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Pozder et al. (US Pub. 2005/0275017).
Regarding claim 1, Pozder teaches a method comprising:
forming first integrated circuit devices 414 and second integrated circuit devices 416 on a semiconductor substrate 407 of a wafer 501 (Fig. 6, it is understood that integrated circuit devices include transistors);
forming a first metal layer 511 (note the metal layers in layer 511 in Fig. 5) as a part of the wafer (Fig. 5 - Fig. 6);
forming a transistor 514 comprising a first source/drain region connected to the first integrated circuit devices 414, wherein the transistor 514 is farther away from the semiconductor substrate 407 than the first metal layer 511 (Fig. 6); and
forming an electrical connector 673 on a surface of the wafer 501, wherein the electrical connector 673 is electrically connected to a second source/drain region of the transistor 514 (note that 673 is connected to a second source/drain of the transistor 514 through the electrical path created by the metal layers, vias in layers 605, 411 and 511 and transistors 416 & 516 as shown in Fig. 6).
Regarding claim 4, Pozder teaches the method of claim 1, wherein the transistor 514 is formed on a front side of the wafer 501 (Fig. 5-6).
Regarding claim 5, Pozder teaches the method of claim 4, wherein the electrical connector 673 is on a backside of the wafer 501, and wherein the method further comprises: forming a through-via 619 penetrating through the semiconductor substrate 407, wherein the through-via 619 electrically connects the electrical connector 673 to the second source/drain region of the transistor 514 (Fig. 6).
Regarding claim 6, Pozder teaches the method of claim 5 further comprising: forming a first electrical path connecting the through-via 619 to the second source/drain region; and forming a second electrical path connecting the first source/drain region to the first integrated circuit devices 414, wherein the first electrical path and the second electrical path comprise portions in a plurality of metal layers (Fig. 6).
Regarding claim 8, Pozder teaches wherein the transistor is formed on a backside of the wafer (Fig. 3 & Fig. 6)
Regarding claim 10, Pozder teaches the method of claim 8, wherein the second integrated circuit devices 416 are configured to have power when the first integrated circuit devices are cut from power (Fig. 6).
Regarding claim 21, Pozder teaches a method comprising:
forming integrated circuit devices (414 & 416) at a surface of a semiconductor substrate 407 (Fig. 6, it is understood that integrated circuit devices include transistors);
forming an electrical connector 673 (Fig. 6);
forming a plurality of metal layers (note the metal layers in layers 411 & 605) on the semiconductor substrate 407, wherein the plurality of metal layers comprise an electrical path extending from a topmost end to a bottommost end of the plurality of metal layers (Fig. 6); and
forming a transistor 514 comprising:
a first source/drain region connecting to the electrical connector 673 (Fig. 6); and
a second source/drain region connecting to the integrated circuit devices 414 through the electrical path (Fig. 6).
Regarding claim 25, Pozder teaches the method of claim 21, wherein the transistor is configured to gate a power to the integrated circuit devices (Fig. 6, the transistor is capable of said functionality). Furthermore, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
Regarding claim 27, Pozder teaches the method of claim 21, wherein the integrated circuit devices (414 & 416) are on a front side of the semiconductor substrate, and the transistor 514 is on a backside of the semiconductor substrate (Fig. 6).
Regarding claim 28, Pozder teaches a method comprising:
forming integrated circuit devices (414 & 416) on a surface of a semiconductor substrate 407 (Fig. 6, it is understood that integrated circuit devices include transistors);
forming a plurality of metal layers (note metal layers in layer 411 & 605) over the integrated circuit devices (Fig. 6); and
at a time after the plurality of metal layers are formed, forming a transistor 514, wherein a drain region of the transistor is connected to the integrated circuit devices 514 through a first electrical path in the plurality of metal layers (see Fig. 6, also note Fig. 4-5, where the plurality of metal layers (411 & 605) are formed in wafer 401 first and then bonded/mounted to wafer 502 that has transistor 514), and wherein the transistor 514 is configured to gate a power supply voltage that is on a source region of the transistor (see Fig. 6, the transistor 514 is capable of gating a power supply voltage that is on a power supply voltage of the transistor). Furthermore, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
Regarding claim 29, Pozder teaches the method of claim 28, wherein the semiconductor substrate and the transistor are comprised in a device die 501 (Fig. 6), and the method further comprises: forming an electrical connector 673 electrically connecting to the source region of the transistor 514; forming a second electrical path in the plurality of metal layers; and forming a through-via 607/619 penetrating through the semiconductor substrate 407, wherein a top metal line in a top metal layer (e.g. 639 or 621) of the plurality of metal layers connects the through-via to the source region of the transistor (see Fig. 6).
Regarding claim 30, Pozder teaches the method of claim 28, wherein the transistor 614 is configured to provide power to the integrated circuit devices (514 and/or 516) when the transistor 514 is turned on, and is configured to cut off power to the integrated circuit devices when the transistor is turned off (Fig. 6). Furthermore, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 & 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Pozder as applied to claims 1 & 21 above, and in further view of Yeh et al (US Pub. 2013/0126859).
Regarding claim 2, Pozder is silent on the method of claim 1, wherein the forming the transistor comprises: forming a metal oxide layer as a channel layer; forming a gate dielectric contacting the metal oxide layer; forming a gate electrode contacting the gate dielectric; and forming a source region and a drain region contacting the metal oxide layer. However, Yeh teaches in Fig. 2C wherein forming a transistor comprises: forming a metal oxide layer 102 as a channel layer (Para [0020 & 0057]); forming a gate dielectric 104 contacting the metal oxide layer 102; forming a gate electrode G contacting the gate dielectric 104; and forming a source region S and a drain region D contacting the metal oxide layer. This has the advantage of obtaining a high mobility and high performance transistor. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Pozder with the metal oxide channel, as taught by Yeh, so as to obtain a high performance transistor.
Regarding claims 22-23, Pozder is silent on the method of claim 21, wherein the forming the transistor comprises depositing a metal oxide layer as a channel layer of the transistor (claim 22); and wherein the channel layer comprises InGaZnO (claim 23). However, Yeh teaches in Para [0020 & 0057] wherein a transistor comprises a metal oxide layer as a channel layer and wherein the channel layer comprises InGaZnO. This has the advantage of obtaining a high mobility and high performance transistor. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Pozder with the metal oxide channel, as taught by Yeh, so as to obtain a high performance transistor.
Allowable Subject Matter
Claims 3, 7, 9, 24 & 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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