DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicants’ arguments filed 07-01-2026 have been fully considered but they are not persuasive.
Regarding argument brought against examiners’ rejection of Claim 1
Applicant argues that since Chen allegedly does not disclose the trench capacitor 128 electrically connected to any through via 136 it cannot teach the limitation “wherein the trench capacitor is electrically coupled between the first through-via and the second through-via”
Applicants’ arguments are found to be incommensurate in scope and thusly unpersuasive.
The argument is unpersuasive since the wording of the claim does not require the electrical coupling of the trench to the vias. The limitation “the trench capacitor is electrically coupled between the first through-via and the second through-via” is, by plan meaning interpretation, a trench capacitor electrically coupled to any component physically between two vias.
Even so the reference Chen Para [0037] teaches that 128 is electrically connected to 130b And [0038] teaches that 136 can provide electrical connections to 130b and to 128 when Chen states “Conductive through-vias 136 can provide electrical connections between interconnect structures 130A and 130B and between trench capacitors 128 and semiconductor devices 126.” Therefore, not only does Chen teach the trench being electrically connected to a through via but Fig 1A shows at face value that the trench is physically between two through vias. Applicants argue against the motivation to combine Andry for space utilization efficiency since this motivation allegedly does not motivate power connection to the vias. Examiner disagrees since this power connection system results in improved space utilization in comparison to power connection elements therefore this design of the power nodes connected through TSVs is motivated and results in the power connection of the vias motivated by space efficiency.
Regarding argument brought against examiners’ rejection of Claim 9
Applicant argues that the limitation “package component is free from decoupling capacitors” does not mean ‘not in contact with’ but instead urges the interpretation of “is free from” to mean that a decoupling capacitor ‘is not inside of’. Although examiner believes “is free from” to be broad the reference applied still overcomes this urged interpretation. Since the package component 106 is described as a substrate comprising conductive lines 106A and conductive vias 106B and does not describe a decoupling capacitor inside of 106. Therefore, it would be obvious to not have a decoupling capacitor since they do not teach a decoupling capacitor within 106.
Regarding argument brought against examiners’ rejection of Claim 11
Due to the similarity to the rejection of Claim 1 see the arguments above
Regarding argument brought against examiners’ rejection of Claim 14
Chen teaches three trench capacitors and in light of the teachings of Sri at least one of the trench capacitors would be dedicated to the second die and thusly decoupled from the integrated circuits of the first die. In Para [0049] of Sri, they describe that to reduce supply voltage droops and spikes each integrated circuit required their own respective independent decoupling capacitor. Meaning in order for the second die in Chen to be affected by the decoupling capacitor it needs its own dedicated capacitor resulting in all of integrated circuits in the first device die to be electrically decoupled from at least one of the trench capacitors making it the trench capacitor. Examiner concedes that the initial rejection may have resulted in some confusion and hopes to bring further clarification to the rejection but nevertheless maintains and finds the argument presented to be unpersuasive.
Regarding argument brought against examiners’ rejection of Claim 15 and 18
Due to the similarity to the rejection of Claim 14 see the arguments above
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 9-13, 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, and further in view of Paul S. Andry et al. (US 20080284037 A1) herein after referred to as “Andry”.
Regarding claim 1, Chen teaches
A method comprising:
forming first integrated circuits (Fig 11 elements126) on a front side (Para. [0037]) of a semiconductor substrate (124) of a first device die (104A);
forming a trench capacitor (128) extending from a backside of the semiconductor substrate into the semiconductor substrate (Para. [0037]);
forming a first through-via and a second through-via (136) penetrating through the semiconductor substrate (Fig 11), wherein the trench capacitor is electrically coupled between the first through-via and the second through-via (para [0038], [0037]); and
bonding a second device die (102A) to the first device die, wherein the second device die comprises second integrated circuits (Para. [0032]).
Chen does not explicitly teach
wherein power nodes of the second integrated circuits are electrically coupled to the first through-via and the second through-via.
Andry teaches a microelectronic packaging of semiconductor chips wherein power nodes (Fig 4 elements 44a and 44b) of the second integrated circuits (41) are electrically coupled to the first through-via and the second through-via.(42c)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Chen such that the power nodes of the second integrated circuits are electrically coupled to the first through-via and the second through-via, as described in Andry because the modification allows for increased space utilization efficiency by having the nodes be a high density array of micro C4 power nodes (Andry Para [0034]).
Regarding claim 2, Chen in view of Andry teaches
The method of claim 1,
Chen further teaches
wherein the second device die is free from decoupling capacitors used for regulating power. (102A does not touch 128)
Regarding claim 3, Chen in view of Andry teaches
The method of claim 1,
Chen further teaches
wherein the second device die (Fig 11 elements 102A) is bonded over the first device die (104A), and wherein the trench capacitor (128) overlaps a part of the first integrated circuits. (126)
Regarding claim 4, Chen in view of Andry teaches
The method of claim 1,
Chen does not describe
wherein the first through-via is electrically connected to electrical ground, and the second through-via is electrically connected to VDD.
Andry further teaches
wherein the first through-via (Fig 4 elements 42c on the left) is electrically connected to electrical ground (45a GND), and the second through-via (42c on the right) is electrically connected to VDD (45b).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Chen such that the first through-via is electrically connected to electrical ground, and the second through-via is electrically connected to VDD, as described in Andry because the modification allows for the efficient power redistribution. (Andry Para. [0035])
Regarding claim 5, Chen in view of Andry teaches
The method of claim 1
Chen further teaches
further comprising: placing the first device die over a carrier (Fig. 11 elements 1024), wherein the front side of the semiconductor substrate faces the carrier (Para. [0037] Fig. 11); forming gap-filling regions (104C) around the first device die (104A); and performing a thinning process to thin the semiconductor substrate (Para. [0053]).
Regarding claim 9, Chen in view of Andry teaches
The method of claim 1
Chen further teaches
further comprising bonding a package component (Fig 1A elements106) to the first device die(104A), wherein the package component is free from decoupling capacitors therein. (106 is not described to have a decoupling capacitor inside of itself)
Regarding claim 10, Chen in view of Andry teaches
The method of claim 1,
Chen further teaches
The method of claim 1, wherein the second integrated circuits (Para. [0032]) in the second device die (102A) are configured to use a power that is regulated by the trench capacitor. (Para [0039])
Regarding claim 11, Chen teaches
A structure comprising:
a first device die (Fig 11 elements104A) comprising:
a semiconductor substrate (124); first integrated circuits (126) at a bottom surface of the semiconductor substrate (126 is on the lower most surface of 124);
a first through-via and a second through-via (136) penetrating through the semiconductor substrate (fig 11); and
a trench capacitor (128) extending from a top surface (fig 11) of the semiconductor substrate into the semiconductor substrate, wherein the trench capacitor is electrically coupled to the first through-via and the second through-via (para [0037],[0038]); and
a second device die(102A) over and bonding to the first device die, wherein the second device die comprises second integrated circuits (Para. [0032] refers to 102A as an active IC die),
Chen does not describe
and a power node of the second integrated circuit is connected to at least one of the first through-via and the second through-via.
Andry Teaches
and a power node (Fig. 4 elements 44a or 44b) of the second integrated circuit (41) is connected to at least one of the first through-via and the second through-via(42c).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Chen such that power node of the second integrated circuit is connected to at least one of the first through-via and the second through-via, as described in Andry because the modification allows for increased space utilization efficiency by having the nodes be a high density array of micro C4 power nodes (Andry (Para [0034]).
Regarding claim 12, Chen in view of Andry teaches
The structure of claim 11,
Chen does not describe
wherein the power node comprises a VDD node and a VSS node.
Andry further teaches
wherein the power node comprises a VDD node (Fig. 4 elements 45b and 44b) and a VSS node (45a and 44a).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Chen such that the power node comprises a VDD node and a VSS node, as described in Andry because the modification allows for the redistribution of lower pitch voltage and lower pitch ground. (Andry Para [0035])
Regarding claim 13, Chen in view of Andry teaches
The structure of claim 11,
Chen further teaches
wherein the second device die (102A) is free from decoupling capacitor (128) that is inside the second device die and is used for regulating power therein. (102A have 128 inside of itself Para[0039] Fig 1A)
Regarding claim 16, Chen in view of Andry teaches
The structure of claim 11,
Chen does not describe
wherein two power nodes of the second integrated circuits are connected to the first through-via and the second through-via
Andry further teaches
wherein two power nodes (Fig 4 elements 44a and 44b) of the second integrated circuits (41) are connected to the first through-via and the second through-via (42c).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Chen such that the two power nodes of the second integrated circuits are connected to the first through-via and the second through-via, as described in Andry because the modification allows for the allows for increased space utilization efficiency by having the nodes be a high density array of micro C4 power nodes (Andry Para [0034]).
Regarding claim 17, Chen in view of Andry teaches
The structure of claim 16,
Chen further teaches
wherein the first integrated circuits (fig. 11 elements 126) comprises a part in a lower part of a portion of the semiconductor substrate (124), and the trench capacitor (128) occupies an upper part of the portion of the semiconductor substrate (124).(Fig. 11)
Claim(s)14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Andry as applied to claim 11 above, and further in view of Archanna Srinivasan et al. (US 20210313991 A1) herein after referred to as “Sri”
Regarding claim 14 Chen in view of Andry teaches
The structure of claim 11,
Chen does not describe
wherein all of integrated circuits in the first device die are electrically decoupled from the trench capacitor.
Sri teaches
wherein all of integrated circuits (circuits of both base IC dies 312-314) in the first device die are electrically decoupled from the trench capacitor (721-723 a decoupling capacitor has been shown to be a trench capacitor above).( Para [0049] fig 7)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Chen in view of Andry such that the all of integrated circuits in the first device die are electrically decoupled from the trench capacitor, as described in Sri because the modification allows for the reduction of supply voltage droops and spikes in the active IC die. (Para. [0049])
Regarding Claim 15 Chen in view of Andry teaches
The structure of claim 11,
Chen does not describe
wherein the first integrated circuits are electrically decoupled from the trench capacitor.
Sri teaches
wherein the first integrated circuits (circuits of both base IC dies 312-314) are electrically decoupled from the trench capacitor. (721-723 a decoupling capacitor has been shown to be a trench capacitor above). (Para [0049] fig 7)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Chen in view of Andry such that the first integrated circuits are electrically decoupled from the trench capacitor, as described in Sri because the modification allows for the reduction of supply voltage droops and spikes in the active IC die. (Para. [0049])
Claim(s) 6, 7, 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Andry as applied to claim 5 above, and further in view of Changyok Park et al. (US 20210375551 A1) herein after referred to as “Park”.
Regarding Claim 6 Chen in view of Andry teaches
The method of claim 5,
Chen further teaches
further comprising, after the thinning process (Para. [0053])., creating the semiconductor substrate from the backside of the semiconductor substrate to form deep trenches (Para. [0037]), wherein the trench capacitor extends into the deep trenches. (Fig. 11)
Chen does not explicitly mention
etching being the process of creating the deep trenches
Park teaches
etching the semiconductor substrate to form deep trenches (Para [0038] process 102 fig. 2A)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Chen such that the process of creating deep trenches is etching, as described in Park because the modification allows for the precision etching is known for and to remove some or all of the dielectric material. (Para [0038])
Regarding Claim 7 Chen in view of Andry teaches
The method of claim 5,
Chen further teaches
wherein the first through-via and the second through-via (Fig 8 element136) are formed before the first device die is placed over the carrier (fig 8 and 10 para [0053],
Chen does teach
the thinning of the substrate but not after the formation of the through vias.
Park teaches
and the thinning process (process 120 Fig 1 and 2j) is performed until the first through-via and the second through-via are exposed.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Chen in view of Andry such that the thinning process is performed until the first through-via and the second through-via are exposed, as described in Park because the modification allows for the TSVs to extend between front and back sides so that an they may be electrically connected (Fig 1 Para [0046])
Regarding Claim 8 Chen in view of Andry teaches
The method of claim 5,
Chen further teaches
further comprising: after the thinning process (Para. [0053]), forming the first through-via and the second through-via penetrating through the semiconductor substrate (Fig 8 Para [0053])
Chen does not explicitly teach
the etching of the through openings.
Park teaches
further etching (process 102) the semiconductor substrate to form through-openings (fig 2A elements 222-1 and 222-2) penetrating through the semiconductor substrate (202), wherein the first through-via and the second through-via are formed in the through-openings. (para [0032])
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Chen in view of Andry such that after the thinning process, further etching the semiconductor substrate to form through-openings penetrating through the semiconductor substrate, wherein the first through-via and the second through-via are formed in the through-openings, as described in view of Park because the modification allows for the for the precision etching is known for and to remove some or all of the unwanted material. (Para [0032])
Claim(s)18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Sri.
Regarding claim 18 Chen teaches
A structure (Fig 11) comprising:
a first device die (104A) comprising:
a semiconductor substrate (124) ;
first integrated circuits (126) close to a bottom surface of the semiconductor substrate (124); and
a trench capacitor (128) , wherein a first portion of the first integrated circuits (bottom portion) and a first portion of the trench capacitor (top portion) are on opposing sides of the semiconductor substrate (are on opposite sides of 124), and wherein a second portion of the first integrated circuits and a second portion of the trench capacitor are in the semiconductor substrate(both 126 and 128 are in the substrate Fig 11); and
a second device die (102A) over and bonding to the first device die, wherein the second device die comprises second integrated circuits (Para. [0032] refers to 102A as an active IC die) electrically coupling to the trench capacitor. (Para. [0048] says trench capacitors can reduce power supply noise to its active dies).
Chen does not describe
wherein the trench capacitor is electrically decoupled from all integrated circuits in the first device die,
Sri teaches
wherein the trench capacitor (721-723 a decoupling capacitor has been shown to be a trench capacitor above). (Para [0049] fig 7) is electrically decoupled from all integrated circuits (circuits of both base IC die 312-314) in the first device die,
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Chen such that the trench capacitor is electrically decoupled from all integrated circuits in the first device die, as described in Sri because the modification allows for the reduction of supply voltage droops and spikes in the active IC die. (Para. [0049])
Claim(s)19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Sri in view of Andry
Regarding claim 19, Chen in view of Sri teaches
The structure of claim 18, wherein the trench capacitor (Chen128) is a decoupling capacitor (Chen Para. [0039])
Chen in view of Sri does not explicitly describe
electrically coupled to a power node of the second integrated circuits.
Andry teaches
wherein the trench capacitor (Fig 4 elements 48) is a decoupling capacitor (Para. [0036]) electrically coupled to a power node of the second integrated circuits. (para [0036] and fig 4).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Chen in view of Sri such that the trench capacitor is a decoupling capacitor electrically coupled to a power node of the second integrated circuits., as described in Andry because the modification allows for the modification allows for the redistribution of lower pitch voltage and lower pitch ground. (Andry Para [0035])
Claim(s)20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Sri in view of Chia-Ming Hung et al. (US 20230282726 A1) herein after referred to as Hung
Regarding claim 20, Chen in view of Sri teaches
The structure of claim 18 further comprising a first through-via and a second through-via (Chen 136) penetrating through the semiconductor substrate (Chen Fig 11),
Chen in view of Sri does not describe
wherein a first capacitor electrode and a second capacitor electrode of the trench capacitor are connected to the first through-via and the second through-via, respectively.
Hung teaches a semiconductor device of integrated circuits
wherein a first capacitor electrode (152) and a second capacitor electrode (153) of the trench capacitor (150) are connected to the first through-via (143 connected to 152) and the second through-via (144 connected to 153), respectively. (Para [0038],[0039])
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Chen in view of Sri such that a first capacitor electrode and a second capacitor electrode of the trench capacitor are connected to the first through-via and the second through-via, respectively, as described in Hung because the modification allows for the electrodes to be electrically connected to at least the second IC circuit (Hung Para [0038],[0039])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yu; Chen-Hua (US-20250266363-A1), Yu; Chen-Hua (US-20230369302-A1).
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Friday, 9:00a.m. - 5:00p.m. ET..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, SUE PURVIS can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAIME LYNN SPRENGER/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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