DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Applicant’s election without traverse of Group I, Species 1, as shown in FIGs. 1A-2 and 8, in the reply filed on July 14, 2026 is acknowledged.
Amendment filed July 14, 2026 is acknowledged. New claims 21-25 have been added. Claims 11-15 have been cancelled. Claims 1-10 and 16-25 are pending.
Action on merits of Elected Invention and/or Species, claims 1-10 and 16-25 follows.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 02, 2024 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
A SEMICONDUCTOR DEVICE STRUCTURE HAVING A CONDUCTIVE VIA (TSV) EXTENDING THROUGHT A SUBSTRATE WITH ENLARGED PORTIONS ON TOP AND BOTTOM OF THE VIA
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-10, 16 and 19-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE et al. (US. Pub. No. 2012/0056330).
With respect to claim 1, LEE teaches a semiconductor device structure as claimed including:
a chip structure comprising a substrate (10) and a wiring structure (40) over a first surface of the substrate (10), wherein the chip structure has a hole (21) penetrating through the wiring structure (40) and the substrate (10), the hole (21) has a first enlarged portion (top), a second enlarged portion (50), and a neck portion (D1) between the first enlarged portion (top) and the second enlarged portion (50), the first enlarged portion (top) is wider than the neck portion (D1), and the second enlarged portion (50) is wider than the neck portion (D1);
a first seed layer (barrier pattern, not shown) over the wiring structure (40), a first inner wall (23) of the first enlarged portion (top), and a second inner wall (23) of the neck portion (D1); and
a second seed layer (barrier pattern, not shown) over a second surface (bottom) of the substrate (10), a third inner wall (52) of the second enlarged portion (50), and the first seed layer (barrier pattern, not shown) over the second inner wall of the neck portion (D1), wherein the second seed layer is in direct contact with the first seed layer. (See FIG. 13).
With respect to claim 16, LEE teaches a semiconductor device structure, as claimed including:
a chip structure comprising a substrate (10) and a wiring structure (40) over a first surface of the substrate, wherein the chip structure has a hole (21) penetrating through the wiring structure (40) and the substrate (10), the hole has a first enlarged portion (top), a second enlarged portion (50), and a neck portion (D1) between the first enlarged portion and the second enlarged portion, the first enlarged portion (top) is wider than the neck portion (D1), the second enlarged portion (50) is wider than the neck portion (D1), the hole has a first shape in a top view of the chip structure, the hole has a second shape in a bottom view of the chip structure, and the first shape is different from the second shape; and
a seed layer (barrier pattern, not shown) over the wiring structure, a first inner wall of the first enlarged portion (top), a second inner wall of the neck portion (D1), a third inner wall of the second enlarged portion (50), and a second surface (bottom) of the substrate. (See FIG. 13).
With respect to claim 21, LEE teaches a semiconductor device structure, as claimed including:
a chip structure comprising a substrate (10) and a wiring structure (40) over a first surface (top) of the substrate, wherein the chip structure has a hole (21) penetrating through the wiring structure (40) and the substrate (10), the hole (21) has a first enlarged portion (top), a second enlarged portion (50), and a neck portion (D1) between the first enlarged portion (top) and the second enlarged portion (50), the first enlarged portion (top) is wider than the neck portion (D1), and the second enlarged portion (50) is wider than the neck portion (D1);
a first seed layer (barrier pattern, not shown) over the wiring structure, a first inner wall of the first enlarged portion (top), and a second inner wall of the neck portion (D1); and
a second seed layer (barrier pattern, not shown) over a second surface (bottom) of the substrate, a third inner wall of the second enlarged portion (50), and the first seed layer over the second inner wall of the neck portion (D1), wherein the first seed layer has a first portion and a second portion, the first portion is covered by the second seed layer, the second portion is not covered by the second seed layer, the second seed layer has a third portion and a fourth portion, the third portion covers the first portion, the fourth portion does not cover the first seed layer, and the third portion is thinner than the fourth portion. (See FIG. 13).
Product by process limitation:
The expression “wherein the first seed layer has a first portion and a second portion, the first portion is covered by the second seed layer, the second portion is not covered by the second seed layer, the second seed layer has a third portion and a fourth portion, the third portion covers the first portion, the fourth portion does not cover the first seed layer, and the third portion is thinner than the fourth portion” is/are taken to be a product by process limitation and is given no patentable weight. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al., 218 USPQ 289, 292 (Fed. Cir. 1983); In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old and obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
Note that Applicant has burden of proof in such cases as the above case law makes clear.
Insofar as the structure is concerned, since the “second seed layer” is grown on the “first seed layer” utilizing the same material, the seed layers are merged together, thin portion or the thick portion are eliminated.
Since, the second seed layer of LEE is formed on the first seed layer, limitation is met.
With respect to claim 2, the first seed layer (barrier pattern) of LEE has a first portion and a second portion, the first portion is covered by the second seed layer, the second portion is not covered by the second seed layer, and the first portion is thinner than the second portion.
Product by process limitation:
The expression “the first seed layer has a first portion and a second portion, the first portion is covered by the second seed layer, the second portion is not covered by the second seed layer, and the first portion is thinner than the second portion” is/are taken to be a product by process limitation and is given no patentable weight. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al., 218 USPQ 289, 292 (Fed. Cir. 1983); In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old and obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
Note that Applicant has burden of proof in such cases as the above case law makes clear.
Insofar as the structure is concerned, since the “second seed layer” is grown on the “first seed layer” utilizing the same material, the seed layers are merged together, thin portion or the thick portion are eliminated.
Since, the second seed layer of LEE is formed on the first seed layer, limitation is met.
With respect to claims 3 and 22, As best understood by the Examiner, as discussed above, as a structure, the seed layers are merged. Thus, the limitation a thickness of the first portion decreases toward the second surface of the substrate is met.
With respect to claim 4, the hole (21) of LEE has a shape in a bottom view of the chip structure, and the shape comprises a flower-like shape.
Note that, the hole with flower-like shape would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
With respect to claim 7, the first seed layer (barrier pattern, not shown) of LEE conformally covers the wiring structure, the first inner wall of the first enlarged portion (top), and the second inner wall of the neck portion (D1).
With respect to claim 8, the second seed layer (barrier pattern) of LEE conformally covers the second surface of the substrate (bottom) and the third inner wall of the second enlarged portion (50).
With respect to claim 9, the semiconductor device structure of LEE further comprises: a first wiring layer (40) over the first seed layer. (See FIG. 11).
With respect to claim 10, the semiconductor device structure of LEE further comprises: a second wiring layer over the second seed layer.
With respect to claim 19, the second shape of the hole (21) of LEE comprises a flower-like shape.
Note that, the hole with flower-like shape would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
With respect to claim 20, the seed layer (barrier pattern) of LEE comprises: a first seed layer over the wiring structure, the first inner wall of the first enlarged portion (top), and the second inner wall of the neck portion (D1); and a second seed layer (barrier pattern) over the second surface (bottom) of the substrate, the third inner wall of the second enlarged portion (50), and the first seed layer over the second inner wall of the neck portion (D1).
With respect to claim 23, the first portion of the first seed layer of LEE is between the third portion of the second seed layer and the substrate.
With respect to claim 24, a first sidewall of the second portion of the first seed layer of LEE is substantially level with and connected to a second sidewall of the third portion of the second seed layer.
With respect to claim 25, the second inner wall of the neck portion (D1) of LEE is covered by the first portion of the first seed layer and the third portion of the second seed layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over LEE ‘330 as applied to claims 1 and 16 above, and further in view of MARIMUTHU et al. (US. Pub. No. 2010/0133704).
With respect to claims 5 and 17, LEE teaches the semiconductor device structure as described in claim 1 and 16 above including the second inner wall of the neck portion (D1) is steep with respect to the first surface of the substrate.
Thus, LEE is shown to teach all the features of the claim with the exception of explicitly disclosing the second inner wall of the neck portion is steep er than the first inner wall of the first enlarged portion.
However, MARIMUTHU teaches a semiconductor device structure including a second inner wall of the neck portion (212) is steeper than the first inner wall of the first enlarged portion (231) with respect to the first surface of the substrate. (See FIG. 5e).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the second inner wall of the neck portion of LEE being steeper than the first inner wall of the first enlarged portion with respect to the first surface of the substrate as taught by MARIMUTHU for the same intended purpose of enlarging the first enlarge portion, without departing from the scope of either.
With respect to claims 6 and 18, in view of MARIMUTHU, the second inner wall of the neck portion (212) is steeper than the third inner wall of the second enlarged portion (222) with respect to the second surface of the substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710. (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANH D MAI/ Primary Examiner, Art Unit 2893
Prosecution Insights