Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/19/2024 and 10/21/2024 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yun et al, US 20220301943.
Yun teaches:
A method comprising:
forming a plurality of nanowires (310) over semiconductor fins in both an n-type region (102) and in a p-type region (104);
forming a hard mask layer (336) over a first set of the plurality of nanowires in the n- type region;
performing a trimming process (para 62) on a second set of the plurality of nanowires in the p-type region;
depositing silicon germanium (312) over each one nanowires of the second set of the plurality of nanowires; and
performing an annealing (para 61) process on the second set of the plurality of nanowires, wherein the annealing process diffuses germanium into at least one of the second set of the plurality of nanowires forming a plurality of silicon germanium nanostructures in the p-type region, wherein the plurality of silicon germanium nanostructures have different regions of varying germanium concentrations. (para 60, 61) Figure 16A and 16B
17. The method of claim 16, wherein the depositing silicon germanium and the annealing process occur in a same chemical vapor deposition chamber. (para 60,61)
18. The method of claim 16, wherein the plurality of nanowires comprises silicon and the annealing process diffuses up to about 20% concentration of germanium into a center of at least one of the second set of the plurality of nanowires. (para 61)
19. The method of claim 16, wherein the depositing silicon germanium is performed at a first temperature and the performing the annealing process occurs at a second temperature greater than the first temperature (para 44, and 60)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al, US 20220301943 in view of Yeong et al, US 20210175129 A1 and in further view of TW 202009988 A.
Yun teaches:
A device comprising:
a plurality of silicon nanostructures (310) above a semiconductor substrate in an n- type region (102) of the semiconductor substrate (302);
a plurality of silicon germanium nanostructures (312) above the semiconductor substrate in a p-type region (104) of the semiconductor substrate (302). See figure 8B
Yun fails to teach:
a high-k dielectric layer surrounding at least one of the plurality of silicon nanostructures and at least one of the plurality of silicon germanium nanostructures;
and
a gate electrode filling in a gap between adjacent ones of the plurality of silicon germanium nanostructures.
Yeong teaches:
[0049] As illustrated in FIGS. 14A and 14B, portions of the high-k dielectric layer 220 respectively surround the first interfacial layers 210a and can be referred to as first high-k dielectric linings 220a, and other portions of the high-k dielectric layer 220 respectively surround the second interfacial layers 210b and can be referred to as second high-k dielectric linings 220b. Portions of the first high-k dielectric sheath layers 230 respectively surround the first high-k dielectric linings 220a and can be referred to as first high-k dielectric sheaths 230a, and portions of the second high-k dielectric sheath layers 250 respectively surround the second high-k dielectric linings 220b and can be referred to as second high-k dielectric sheaths 250b. A portion of the metal layer 260 surrounds the first high-k dielectric sheaths 230a and can be referred to as a first metal gate electrode 260a, and a portion of the metal layer 260 surrounds the second high-k dielectric sheaths 250b and can be referred to as a second metal gate electrode 260b.
[0050] The first interfacial layers 210a, first high-k dielectric linings 220a, first high-k dielectric sheaths 230a, and first metal gate electrode 260a can be in combination serve as a first gate stack GS1 for the first nanowires 108A. The second interfacial layers 210b, second high-k dielectric linings 220b, second high-k dielectric sheaths 250b, and second metal gate electrode 260b can be in combination serve as a second gate stack GS2 for the second nanowires 108B.
Yun and Yeong fail to teach:
wherein at least one of the plurality of silicon germanium nanostructures comprises:
a silicon core region having a first concentration of germanium, wherein the first concentration of germanium is about 20% or less;
a first silicon germanium region having a first interface between the silicon core region and the first silicon germanium region; and
a second silicon germanium region having a second interface between the first silicon germanium region and the second silicon germanium region, the second silicon germanium region having a second concentration of germanium, wherein the second concentration of germanium is up to about 40%; wherein a first concentration gradient of germanium increases from the first concentration of germanium at the first interface to the second concentration of germanium at the second interface;
Yun teaches: (para 39)
In various embodiments, the semiconductor layers 312 have compositions that provide for different oxidation rates and/or different etch selectivity from the semiconductor layers 310. In an embodiment, the semiconductor layers 312 include silicon germanium (Si.sub.1-xGe.sub.x), while the semiconductor layers 310 include silicon (Si). In some embodiments, each layer 312 is Si.sub.1-xGe.sub.x that includes about 10% to about 100% (0.1≤x≤1) Ge in molar ratio. A sufficient amount of Ge in each layer 312 helps convert the channel region 128 in the fin 104 from a first-type (e.g., n-type) to a second-type (e.g., p-type). For example, Ge may comprise about 60% to about 80% of the layer 312 of Si.sub.1-xGe.sub.x in molar ratio. Such a range of Ge, combined with subsequent processing steps, effectively converts the channel region 128 from the first-type to the second-type. Further, the semiconductor layers 312 may include different compositions among them.
TW 202009988 A teaches:
In FIG. 7, the first thin layer 205 of the superlattice 203 (for example, a thin layer of silicon germanium) can be formed as the first tapered layer of two or more gradient layers of the same semiconductor material 700, each gradient layer has a concentration percentage of semiconductor material elements. In one embodiment, as shown in FIG. 7, the first tapered layer 700 may be formed as a tapered layer of a first semiconductor material (eg, silicon germanium), including a first gradient layer 701 having a first gradient percentage (For example: silicon germanium with a first percentage of germanium), a second gradient layer 703 with a second gradient percentage (for example: a silicon germanium with a second percentage of germanium), and a third gradient percentage with a third gradient Three gradient layers 705 (for example: silicon germanium with a third percentage of germanium). See English translation
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to combine the above references, because a multi-layer structure is formed including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. (abstract TW 202009988 A)
In regards to the concentration ranges, it would have been obvious to one of ordinary skill in the art to optimize these values though routine experimentation and would not lend itself to patentability in the instant application without displaying unexpected results. (in Re Aller)
TW 202009988 A further teaches:
2.The device of claim 1, wherein the at least one of the plurality of silicon germanium nanostructures further comprises a third silicon germanium region having a third interface between the second silicon germanium region and the third silicon germanium region and an exterior surface opposite the third interface, wherein a second concentration gradient of germanium decreases from the second concentration of germanium at the third interface to about 0% germanium at the exterior surface.
(see figure 7)
3.The device of claim 1, wherein the gap between at least one of the plurality of
silicon germanium nanostructures is in a range of about 3 nm to about 10 nm.
In regards to the thickness ranges, it would have been obvious to one of ordinary skill in the art to optimize these values though routine experimentation and would not lend itself to patentability in the instant application without displaying unexpected results. (in Re Aller)
4.The device of claim 1, wherein respective ones of the plurality of silicon
nanostructures has a same width as respective ones of the plurality of silicon
germanium nanostructures.
In regards to the width ranges, it would have been obvious to one of ordinary skill in the art to optimize these values though routine experimentation and would not lend itself to patentability in the instant application without displaying unexpected results. (in Re Aller)
TW 202009988 A further teaches:
5. The device of claim 1, further comprising a silicon cap layer (207) surrounding at least one of the plurality of silicon germanium nanostructures. Figure 8
6. The device of claim 5, wherein the silicon cap layer has a thickness in a range
about .5 nm to about 2 nm.
In regards to the thickness ranges, it would have been obvious to one of ordinary skill in the art to optimize these values though routine experimentation and would not lend itself to patentability in the instant application without displaying unexpected results. (in Re Aller)
Yeong further teaches
7. The device of claim 1, further comprising an interface layer (210) disposed between at least one of the silicon germanium nanostructures and the high-k dielectric layer (230), wherein the interface layer comprises silicon oxide. Figure 14B and para 50
Yun et al further teaches:
8. The device of claim 1, further comprising a dielectric structure (324) disposed between the n-type region and the p-type region, wherein the dielectric structure (324) electrically isolates the plurality of silicon nanostructures from the plurality of silicon germanium nanostructures. Figure 8B
Yun teaches:
9. A method comprising:
forming a plurality of silicon nanostructures (310) above a semiconductor substrate (302) in an n-type region (102) of the semiconductor substrate;
forming a plurality of silicon germanium nanostructures (312) above the semiconductor substrate (302) in a p-type region (104) of the semiconductor substrate, See figure 8B
Yun fails to teach:
depositing a high-k dielectric layer surrounding at least one of the plurality of silicon nanostructures and at least one of the plurality of silicon germanium nanostructures; and
forming a gate electrode filling in a gap between adjacent ones of the plurality of silicon germanium nanostructures. See figure 14 and para 49, 50
Yeong teaches:
depositing a high-k dielectric layer (230) surrounding at least one of the plurality of silicon nanostructures (108a) and at least one of the plurality of silicon germanium nanostructures (108b); and
forming a gate electrode (260) filling in a gap between adjacent ones of the plurality of silicon germanium nanostructures. See figure 14 and para 49, 50
Yun and Yeong fail to teach:
wherein at least one of the plurality of silicon germanium nanostructures comprises:
a silicon core region having a first concentration of germanium, wherein the first concentration of germanium is about 20% or less;
a first silicon germanium region having a first interface between the silicon core region and the first silicon germanium region; and
a second silicon germanium region having a second interface between the first silicon germanium region and the second silicon germanium region, the second silicon germanium region having a second concentration of germanium, wherein the second concentration of germanium is up to about 40%; wherein a first concentration gradient of germanium increases from the first concentration of germanium at the first interface to the second concentration of germanium at the second interface.
Yun teaches: (para 39)
In various embodiments, the semiconductor layers 312 have compositions that provide for different oxidation rates and/or different etch selectivity from the semiconductor layers 310. In an embodiment, the semiconductor layers 312 include silicon germanium (Si.sub.1-xGe.sub.x), while the semiconductor layers 310 include silicon (Si). In some embodiments, each layer 312 is Si.sub.1-xGe.sub.x that includes about 10% to about 100% (0.1≤x≤1) Ge in molar ratio. A sufficient amount of Ge in each layer 312 helps convert the channel region 128 in the fin 104 from a first-type (e.g., n-type) to a second-type (e.g., p-type). For example, Ge may comprise about 60% to about 80% of the layer 312 of Si.sub.1-xGe.sub.x in molar ratio. Such a range of Ge, combined with subsequent processing steps, effectively converts the channel region 128 from the first-type to the second-type. Further, the semiconductor layers 312 may include different compositions among them.
TW 202009988 A teaches:
In FIG. 7, the first thin layer 205 of the superlattice 203 (for example, a thin layer of silicon germanium) can be formed as the first tapered layer of two or more gradient layers of the same semiconductor material 700, each gradient layer has a concentration percentage of semiconductor material elements. In one embodiment, as shown in FIG. 7, the first tapered layer 700 may be formed as a tapered layer of a first semiconductor material (eg, silicon germanium), including a first gradient layer 701 having a first gradient percentage (For example: silicon germanium with a first percentage of germanium), a second gradient layer 703 with a second gradient percentage (for example: a silicon germanium with a second percentage of germanium), and a third gradient percentage with a third gradient Three gradient layers 705 (for example: silicon germanium with a third percentage of germanium). See English translation
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to combine the above references, because a multi-layer structure is formed including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. (abstract TW 202009988 A)
In regards to the concentration ranges, it would have been obvious to one of ordinary skill in the art to optimize these values though routine experimentation and would not lend itself to patentability in the instant application without displaying unexpected results. (in Re Aller)
TW 202009988 A further teaches:
10. The method of claim 9, wherein the at least one of the plurality of silicon germanium nanostructures further comprises a third silicon germanium region having a third interface between the second silicon germanium region and the third silicon germanium region and an exterior surface opposite the third interface, wherein a second concentration gradient of germanium decreases from the second concentration of germanium at the third interface to about 0% germanium at the exterior surface. (see figure 7)
Yun further teaches:
11. The method of claim 10, wherein the forming the plurality of silicon germanium nanostructures comprises:
trimming a plurality of silicon nanostructures above the semiconductor substrate in the p-type region of the semiconductor substrate forming a plurality of trimmed silicon nanostructures (para 66);
depositing silicon germanium over the plurality of trimmed silicon nanostructures (para 60); and
performing an annealing process to diffuse germanium into the plurality of trimmed silicon nanostructures, wherein the annealing process forms the silicon core region, the first silicon germanium region, the second silicon germanium region, and the third silicon germanium region of at least one of the plurality of silicon germanium nanostructures. Para 62
12. The method of claim 11, wherein the depositing silicon germanium is a chemical vapor deposition (CVD) performed in a CVD chamber at a first temperature. (para 62)
13. The method of claim 12, wherein the annealing process is performed in the CVD chamber at a second temperature greater than the first temperature. (para 44)
TW 202009988 A further teaches:
14. The method of claim 9, further comprising forming a silicon cap layer (107)
surrounding at least one of the plurality of silicon germanium nanostructures. See Figure 8
Yeong further teaches
15. The method of claim 9, further comprising forming an interface layer (210) disposed between respective ones of the silicon germanium nanostructures (108) and the high-k dielectric layer (230), wherein the interface layer comprises silicon oxide. See figure 14B and para 50
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al as applied to claim 16 above, and further in view of TW 202009988 A.
TW 202009988 A further teaches:
20. The method of claim 16, further comprising forming a silicon cap layer (107) surrounding at least one of the plurality of silicon germanium nanostructures. See Figure 8
In view of this disclosure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because the silicon cap layer is conventionally formed as a passivation to prevent contaminant degradation.
Conclusion
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/ Primary Examiner, Art Unit 2893
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