Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: TSMP20183561US03
Filling Date: 01/02/2024
Priority Date: 12/5/2018
Inventor: Yu et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Species II, claims 1-3, 7-12 and 14-20 in the reply filed on 11/17/25 is acknowledged.
Applicant’s election of Species II in the reply filed on 11/17/25 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 4-6 and 13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species. The non-elected dependent claims 4-6 and 13 will be rejoined once the elected claims are allowable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tung et al (US 2013/0040423 A1).
Regarding claim 1, Tung discloses a method of forming semiconductor structure (Fig. 2, Paras. 20-25), the method comprising: attaching backsides of a plurality of top dies (element chip 3, Para. 34) to a front side of a wafer (wafer 1), the wafer comprising a plurality of bottom dies (chip 2), the wafer having bonding pads 104 (bottom portion inside 202, Fig. 2C) at the front side of the wafer (wafer 1); forming first conductive pillars 104 (top portion. Inside 106) over the bonding pads of the wafer (wafer 1); forming a dielectric material 106 (Para. 22) over the front side of the wafer around the plurality of top dies (chip 3) and around the first conductive pillars 104; and dicing the wafer (Fig. 2E) to form a plurality of semiconductor structures 212, a semiconductor structure of the plurality of semiconductor structures comprising at least a top die (chip 3), a bottom die (chip 2), and a first conductive pillar 104.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 10, 12, 14-15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Tung et al (US 2013/0040423 A1) in view of Yu et al (US 2017/0373037 A1).
Regarding claim 2, Tung does not explicitly disclose the method of claim 1, further comprising, after dicing the wafer: attaching the semiconductor structure to a carrier; forming second conductive pillars over the carrier adjacent to the semiconductor structure; forming a molding material over the carrier around the semiconductor structure and around the second conductive pillars; and forming a redistribution structure over the molding material.
However, Yu discloses after dicing the wafer (Figs. 7, 11-19): attaching the semiconductor structure 130 (Para. 36) to a carrier (element C, Para. 35); forming second conductive pillars 120 (Para. 15) over the carrier adjacent to the semiconductor structure 130; forming a molding material 140 (Para. 43) over the carrier around the semiconductor structure 130 and around the second conductive pillars 120; and forming a redistribution structure 150 (Para. 47) over the molding material 120 (Para. 47).
Yu teaches the above modification is used to protect by insulation of the device (Para. 45). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Tung structure with Yu molding material as suggested above to protect by insulation of the device (Para. 45).
Regarding claim 3, Tung further discloses the method of claim 2, further comprising, after forming the redistribution structure 150: removing the carrier; after removing the carrier (Para. 51), bonding a semiconductor package 190 (Para. 53) to the second conductive pillars 120; and forming an underfill material (element AD, Para. 36) between the semiconductor package 190 and the molding material 140.
Regarding claim 10, Tung does not explicitly disclose the method of claim 1, wherein attaching the backsides of the plurality of top dies comprises bonding the backsides of the plurality of top dies directly to an outermost dielectric layer of the wafer facing the plurality of top dies.
However, Yu discloses attaching the backsides of the plurality of top dies 110 (Para. 28, Tung shoes plurality) comprises bonding the backsides of the plurality of top dies 110 directly to an outermost dielectric layer 150 (Para. 47, conductive inside the dielectric) of the wafer facing the plurality of top dies 110.
Yu teaches the above modification is used to make connection of the device (Fig. 15). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Tung structure with Yu insulating material as suggested above to make connection of the device (Fig. 15).
Regarding claim 12, Tung discloses a method of forming semiconductor structure (Figs. 1-2, Paras. 20-25), the method comprising: bonding backsides of a plurality of top dies (element chip 3, Para. 34) to a front side of a wafer (wafer 1), the wafer comprising a plurality of bottom dies (chip 2), the plurality of top dies (chip 3) being bonded to a top dielectric layer 106 (Para. 22) of the wafer; forming first conductive pillars 104 (Para. 15) over and electrically coupled to first conductive pads 104 (portion inside element 202) at the front side of the wafer; forming second conductive pillars 104 (on chip 3) over and electrically coupled to second conductive pads 104 (bottom portions) at front sides of the plurality of top dies (chip 3); and performing a dicing process to separate the wafer and form a plurality of semiconductor structures 212 (Fig. 2E), wherein a semiconductor structure of the plurality of semiconductor structures comprises at least a top die (chip 3), a bottom die (chip 2), a first conductive pillar 104 (portion of the direct connection to 202), and a second conductive pillar 104 (direct connection to chip 3).
Tung does not explicitly disclose forming a dielectric material over the front side of the wafer and around the plurality of top dies.
However, Yu discloses forming a dielectric material 140 (Figs. 1-19) over the front side of the wafer (Fig. 15) and around the plurality of top dies 110.
Yu teaches the above modification is used to protect by insulation of the device (Para. 45). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Tung structure with Yu molding material as suggested above to protect by insulation of the device (Para. 45).
Regarding claim 14, Tung discloses the method of claim 12, wherein the second conductive pillars 104 are formed over the second conductive pads after the backsides of the plurality of top dies (chip 3) are bonded to the front side of the wafer (Figs. 1, 2).
Regarding claim 15, Tung discloses the method of claim 14, wherein the first conductive pillars 104 and the second conductive pillars 104 are formed by a same processing step (Fig. 2).
Regarding claim 16, Yu discloses the method of claim 12, further comprising, before performing the dicing process (Figs, 16-28): forming redistribution structures 150 (Para. 47) over the dielectric material 140 and electrically coupled to the plurality of top dies 110, the first conductive pillars 132b, and the second conductive pillars 120; and forming connectors 160 over and electrically coupled to the redistribution structures 150, wherein after performing the dicing process, the semiconductor structure further comprises a redistribution structure 170 and a connector 172 (Fig. 28).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Tung et al (US 2013/0040423 A1) in view of Yu et al (US 2017/0373037 A1) and Kilger (US 2014/0036464 A1).
Regarding claim 11, Tung does not explicitly disclose the method of claim 1, wherein attaching the backsides of the plurality of top dies comprises: forming a nitride layer along the backsides of the plurality of top dies; and bonding the nitride layer to an outermost dielectric layer of the wafer facing the plurality of top dies.
However, Yu discloses attaching the backsides of the plurality of top dies 110 comprises: forming a dielectric layer 150 (multiple layers) along the backsides of the plurality of top dies 110; and bonding the dielectric layer to an outermost dielectric layer 150 (multilayer) of the wafer facing the plurality of top dies 110.
Yu teaches the above modification is used to make connection of the device (Fig. 15). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Tung structure with Yu insulating material as suggested above to make connection of the device (Fig. 15).
Tung in view of Yu does not explicitly disclose forming a nitride layer along the backsides of the plurality of top dies.
However Kilger discloses the redistribution layer is made out of SiN (Para. 33). Kilger teaches the above modification is used to make connection of the device (Para. 33). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Yu RDL layer 150 material with Kilger RDL material as suggested above to make connection of the device (Para. 33).
Allowable Subject Matter
Claims 7-8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17-19 and 20 are allowed.
The following is an examiner’s statement of reasons for allowance:
The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed method of forming semiconductor structure, the method comprising: removing the probing pads from the bottom wafer; after removing the probing pads, forming bonding pads at the front side of the bottom wafer; attaching backsides of top dies to the front side of the bottom wafer, wherein the bonding pads are exposed by the top dies; forming first conductive pillars on the bonding pads adjacent to the top dies in combination with all other limitations as recited in claim 17.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817