Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
No certified copy of any foreign priority document is part of the file. The foreign document FR1857894 has not been provided – nor has any documentation been submitted as related to the national stage with PCT/FR2019/052026.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered and as to the arguments about the claimed ranges of: a thickness of each of the first and second semiconductor layers is between 25 nm and 40 nm, and a thickness of the second electrically insulating layer is between 10 nm and 30 nm, being described in Reznicek as including many additional ranges outside of the claimed ranges, this argument is respectfully traversed as Reznicek discloses a range that is slightly outside of the claimed range (this can be seen in the new rejection below), but provides a lot of overlap and is not overly large on the non-overlap to be so broad. Therefore, the claimed ranges are deemed as being obvious, as seen in the more descriptive rejection below. Further, in the combination of the amended limitations that were included in amended claim 1, a new reference to Liu et al. US 9202920 is added to the rejection below to teach the specific height of the fin. No dependent claim was separately argued as to the merits, therefore, those claims remain rejected as claim 1 is still rejected.
Claim Objections
Claims 1, 5-9, 15-17, are objected to because of the following informalities: Claims1, 5-9, 15-17 recite "the first semiconductor" and “the second semiconductor. It appears applicant was attempting to deleted 'single crystal' from each of a first and second semiconductor layer, it is recommended if that is what applicant wants to do, they delete those words from "a single crystal first semiconductor layer" and "a single crystal first semiconductor layer" - so throughout the claims there is a consistent "a first semiconductor layer", "the first semiconductor layer", "a second semiconductor layer", and "the second semiconductor layer"
Claim 1 is objected to because of the following informalities: On line 4 of claim 1, applicant states "at least one fin", then on that same line states "each fin", then on the third to last line of the claim states "the at least fin" (which should at least be corrected to "the at least one fin"). But it is recommended to remain consistent to either refer back as "the at least one fin" or "each fin" because they both mean the same thing, but the claim will read better by choosing one phrase and continuing to use the chosen phrase.
Claim 16 is objected to because of the following informalities: Claim 16 recites “the first layer of semiconductor material”. It is recommended to maintain consistency by writing “the first semiconductor layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1, 5-7, 9-13, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek et al. US 9812575 in view of Liu et al. US 9202920.
Regarding claim 1, Reznicek discloses a CFET device, comprising:
a carrier substrate (figures 1 and 2, element 110 is a "a handle substrate" that functions as a carrier substrate - see column 3, lines 4-7)
a first electrically insulating layer on the carrier substrate (figures 1 and 2, first dielectric layer 120 is an insulating layer - see column 3, lines 23-28) and
at least one fin extending vertically from the electrically insulating layer (figure 2, fin stacks 300 extend vertically from the electrically insulating layer 120 - see column 5, lines 18-26),
each fin comprising a single crystal first semiconductor layer (figure 2, each fin 300 comprises a single crystal first semiconductor layer, element 140, formed from layer 140L of figure 1 - see column 5, lines 18-26 and column 6, lines 41-49),
a second electrically insulating layer on the first semiconductor layer, (figure 2, element 150, formed from layer 150L of figure 1 is a dielectric insulating layer - see column 6, lines 41-49 and a single crystal second semiconductor layer (figure 2, element 160, formed from figure 1, layer 160L, may be a single crystal second semiconductor - see column 6, lines 41-49),
and a single crystal second semiconductor layer, wherein a channel of a first transistor in the semiconductor layer has a first conductivity type
and a channel of a second transistor layer in the second semiconductor layer has a second conductivity type, the second conductivity type being opposite the first conductivity type (Reznicek column 9, lines 59-62 discloses that the portion of each semiconductor fin 140 and 160 that is not converted into a source or drain region constitutes a channel region. Reznicek column 4, lines 37-43 discloses that the second semiconductor layer 160L may be doped to have a conductivity opposite to that of 140L; therefore, the channels formed by these layers will be of opposite type.)
Reznicek lacks wherein a height of the at least fin is between 60 nm and 90 nm, a thickness of each of the first and second semiconductor layers is between 25 nm and 40 nm, and a thickness of the second electrically insulating layer is between 10 nm and 30 nm.
However, Liu discloses an analogous fin with a fin height of 60 nm (column 7, lines 45-47).
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to make Reznicek’s fin with a height of 60 nm, to balance considerations of better current flow, and therefore improve performance, for higher and thinner fins with the need to limit parasitic capacitance by limiting fin height.
Reznicek as modified still lacks specifically disclosing a thickness of each of the first and second semiconductor layers is between 25 nm and 40 nm, and a thickness of the second electrically insulating layer is between 10 nm and 30 nm.
As noted above Reznicek teaches the width of the fin ranges from 4nm to 30nm (col 5 lines 33-38, noting that the width of the fin includes the two semiconductor layers and the insulating layer), and in all the figures of Reznicek showing the fin (figures 2-8), the width of each of the two semiconductor layers (160 and 140) as well as the insulating layer (150) have the same width, the width of the fin. MPEP 2144.05 I. Overlapping, Approaching, and Similar Ranges, Amounts, and Proportions states In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (The prior art taught carbon monoxide concentrations of "about 1-5%" while the claim was limited to "more than 5%." The court held that "about 1-5%" allowed for concentrations slightly above 5% thus the ranges overlapped.); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997) (Claim reciting thickness of a protective layer as falling within a range of "50 to 100 Angstroms" considered prima facie obvious in view of prior art reference teaching that "for suitable protection, the thickness of the protective layer should be not less than about 10 nm [i.e., 100 Angstroms]." The court stated that "by stating that ‘suitable protection’ is provided if the protective layer is ‘about’ 100 Angstroms thick, [the prior art reference] directly teaches the use of a thickness within [applicant’s] claimed range."). See also In re Bergen, 120 F.2d 329, 332, 49 USPQ 749, 751-52 (CCPA 1941) (The court found that the overlapping endpoint of the prior art and claimed range was sufficient to support an obviousness rejection, particularly when there was no showing of criticality of the claimed range).
Because Reznicek teaches the width of the fin ranges from 4nm to 30nm (col 5 lines 33-38), there is an overlapping range of 25-30 nm with both the semiconductor limitation of 25 - 40 nm and the insulating limitation of 10-30 nm. In certain instances it would be obvious to a person having ordinary skill in the art before the time of filing for the width of the first semiconductor layer, the electrically insulating layer, and the second semiconductor layer to all have a thickness between 25-30 nm, as this allows for consistency of the width of the fin allowing for a more streamlined (fin of the same width) and cheaper device, while keeping the fin width small enough for sufficient durability allowing for a long lasting, functional semiconductor device. Which reads on the claimed limitation of 25 - 40 nm for the semiconductor layers and 10-30 nm for the electrically insulating layer.
Regarding claim 3, Reznicek discloses a CFET device of claim 1, wherein a thickness of each of the first and second semiconductor layers is between 25 nm and 40 nm (Reznicek column 3, lines 66-67 and column 4, lines 1-3 discloses wherein a thickness of the first semiconductor layer can vary from 5 nm to 150 nm, which encompasses the claimed range of between 25 nm and 40 nm and therefore anticipates the claimed range according to MPEP 2131.03 II. Similarly, Reznicek column 4, lines 39-43 discloses wherein a thickness of the second semiconductor layer can vary between 5 nm to 150 nm, which encompasses the claimed range of between 25 nm and 40 nm and therefore anticipates the claimed range according to MPEP 2131.03 II.)
Regarding claim 5, Reznicek discloses the CFET device of claim 1, wherein the first and second semiconductor layers comprise silicon doped with opposite polarities (Reznicek discloses wherein the second semiconductor layer may be doped to have a conductivity opposite to that of the first semiconductor layer).
Regarding claim 6, Reznicek discloses the CFET device of claim 1, wherein the first and second semiconductor layers comprise silicon having different crystal orientations. (Reznicek column 3, lines 63-65 discloses wherein the first semiconductor layer may be composed of a single crystalline semiconductor material, such as single crystalline silicon. Reznicek column 4, lines 26-32 discloses wherein the second semiconductor layer may be composed of the same material as the first semiconductor layer, i.e. single crystalline silicon. Reznicek column 4, lines 44-47 discloses wherein the second semiconductor layer may have a crystallographic orientation that is different from that of the first semiconductor layer.)
Regarding claim 7, Reznicek discloses the CFET device of claim 1, wherein the first and second semiconductor layers comprise different materials. (Reznicek column 4, lines 26-32 discloses wherein the second semiconductor layer is comprised of any semiconducting material that may different from, that of the first semiconductor layer.)
Regarding claim 9, Reznicek discloses the CFET device of claim 1, wherein one of the first and second semiconductor layers comprises silicon-germanium and a channel of a p-type transistor is disposed in the silicon-germanium. (Reznicek column 4, lines 33-36 discloses that when the first semiconductor layer includes Si, which is suited for n-type FETs, the second semiconductor layer may include SiGe, which is suited for p-type FETs, or vice versa)
Regarding claim 10, Reznicek discloses the CFET device of claim 1, wherein the first electrically insulating layer and/or the second electrically insulating layer comprises silicon oxide (SiO₂). (Reznicek column 3, lines 23-24 discloses wherein the first dielectric layer may include a dielectric material such as silicon dioxide.)
Regarding claim 11, Reznicek discloses the CFET device of claim 1, wherein the first and second electrically insulating layers comprise different materials. (Reznicek column 4, lines 14-16 discloses wherein the second dielectric layer may be comprised of a dielectric material different from that of the first dielectric layer.)
Regarding claim 12, Reznicek discloses the CFET device of claim 1, wherein the first electrically insulating layer comprises a high-k material. (Reznicek column 3, lines 23-26 discloses wherein the first dielectric layer may include silicon nitride, known to be a high-k material, as it has a dielectric constant higher than that of silicon dioxide.)
Regarding claim 13, Reznicek discloses the CFET device of claim 1, wherein the second electrically insulating layer comprises a low-k material. (Reznicek column 4, lines 11-14 discloses wherein the second dielectric layer may include a low-k material.)
Regarding claim 15, Reznicek discloses the CFET device of claim 1, wherein the first semiconductor layer is molecularly bonded to the carrier substrate (The last paragraph of column 4 describes the semiconductor-on-insulator process, a molecular bonding process, being used to
bond the carrier layer 110 the first dielectric layer 130L, and the first semiconductor layer 140L.).
Regarding claim 16, Reznicek discloses the CFET device of claim 15, wherein the second semiconductor layer is molecularly bonded to the first layer of semiconductor material. (The last paragraph of column 4 describes the semiconductor-on-insulator process, a molecular bonding process, being used to bond the first semiconductor layer 140L, the second dielectric layer 150L, and the second semiconductor layer 160L.).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Reznicek in view of Liu et al. US 9202920 as applied to claim 1 above, and further in view of Kato et al. US 20110187410.
Regarding claim 2, Reznicek as modified by Liu discloses the CFET device of claim 1.
Reznicek as modified by Liu lacks wherein the first semiconductor layer has a surface roughness lower than 0.1 nm RMS.
However, Kato discloses a single crystal semiconductor layer grown on a substrate having a root-mean-square surface roughness of preferably less than 0. 1nm [0574].
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to form the substrate and single crystal semiconductor layer on it having a surface roughness lower than 0.1 nm RMS in order to improve device performance and reliability.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Reznicek in view of Liu as applied to claim 1 above, and further in view of in view of Gupta et al. US 20050279992.
Regarding claim 8, Reznicek as modified by Liu discloses the CFET device of claim 1.
Reznicek as modified by Liu lacks wherein one of the first and second semiconductor layers comprises strained silicon and a channel of an n-type transistor is disposed in the strained silicon.
However, Gupta discloses wherein strained silicon semiconductor layers can be formed into components having an n-type channel disposed in the strained silicon [0011].
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to form at least one of the semiconductors where an n-type channel layer was to be formed from strained silicon, SO that the strained silicon channel layer may both provide an n- type channel for some components of a device while also acting as an effective diffusion barrier during processing of the device. [0011], thus producing improved hole mobility [0010].
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Reznicek in view of Liu as applied to claim 1 above, and further in view of Hourai et al. US 20060156969.
Regarding claim 14, Reznicek as modified by Liu discloses the CFET device of claim 1.
Reznicek as modified by Liu lacks wherein the carrier substrate comprises at least one COP-free CZ silicon layer.
However, Hourai discloses a semiconductor substrate comprising at least one COP-free CZ silicon layer [0103 and 0106].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective date of filing to use a substrate comprising at least one COP-free CZ silicon layer to eliminate the effects of the grown-in defects to degrade device electrical characteristics [0103].
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Reznicek in view of Liu as applied to claim 1 above, and further in view of Cheng et al. US 20110127608 .
Regarding claim 17, Reznicek as modified by Liu discloses the CFET device of claim 1.
Reznicek as modified by Liu lacks wherein at least one of the first and second semiconductor layers has a thickness uniformity of +/- 0.5 nm.
However, Cheng discloses a device with a semiconductor layer having a thickness variation of less than 0.5 nm [0040].
Therefore, it would have been obvious to a person of ordinary skill in the art before the time of filing to form semiconductor layers with a thickness uniformity of +/- 0.5 nm in order to achieve compactness while optimizing electrical performance [0002].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Reznicek, Liu, and Cheng, as applied to claim 17 above, and further in view of Zaka et al. US 10283642.
Regarding claim 18, Reznicek as modified by Liu and Cheng discloses the CFET device of claim 17.
Reznicek as modified by Liu and Cheng lacks wherein at least one of the first and second electrically insulating layers has a thickness uniformity of +/- 1 nm.
However, Zaka discloses thickness variation of transistor layers, including insulating layers, of less than approximately 1 nm (see Zaka column 9, lines 34-64).
Therefore, it would have been obvious to a person of ordinary skill in the art before the date of filing to form at least one electrically insulating layer of the CFET device of Reznicek as modified by Cheng to have a thickness uniformity of +/- 1 nm, thereby ensuring low device variability (see Zaka column 9, lines 34-64).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek in view of Liu as applied to claim 1 above, and further in view of in view of Dutartre et al. US 20180166318.
Regarding claim 19, Reznicek as modified by Liu discloses the CFET device of claim 1.
Reznicek as modified by Liu lacks, wherein the carrier substrate comprises a base substrate and at least one functional layer disposed between the base substrate and the first electrically insulating layer.
However, Dutartre discloses a base substrate (figure 6, 1) with a functional layer (figure 6,4 [0046]) disposed between the base substrate and the electrically insulating layer (figure 6, 36 [0061]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to add the functional layer of Dutartre to the base substrate of Reznicek as modified by Liu in order to improve the performance of the device [0005-0014].
Regarding claim 20, Reznicek as modified by Liu and Dutartre discloses the CFET device of claim 19, wherein the at least one functional layer comprises a polysilicon layer (Functional layer 4 of figure 6 comprises a polysilicon layer [0046]).
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights