DETAILED ACTION
This is the Office action based on the 18402328 application filed January 2, 2024, and in response to applicant’s argument/remark filed on June 9, 2026. Claims 1-20 are currently pending and have been considered below. Claims 5, 15 and 20 are withdrawn from consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 6-10, 12-13 and 16-19 rejected under 35 U.S.C. 103 as being unpatentable over Davis et al. (U.S. Pat. No. 8257546), hereinafter “Davis”, in view of Coronel et al. (U.S. Pat. No. 5658418), hereinafter “Coronel”:--Claims 1, 2 : Davis teaches a method of etching a substrate during a semiconductor device fabrication, comprisingproviding a model for the etching comprising (Fig. 1) - measuring dimensions of structures to be formed on a substrate by using ex-situ metrology (Step 12); - determining if the substrate is an outlier by applying an outlier filter (Step 13 and 14); - etching the substrate by using end-point detection by in-situ metrology to form the structure (Step 15). Davis further teaches that the ex-situ metrology comprises critical dimensions (CD), layer thickness, and the like, wherein the outlier filter removes any data points that are outliers and examines the measurement results, such as means, maximum, minimum, standard deviations, goodness of fits and the likes, to determine if the substrate has received good photoresist patterning (Col. 3, Line 27 through Col. 4, Line 39) Davis further teaches that the in-situ metrology comprises spectroscopy, interferometry, scatterometry, reflectometry, optical electromagnetic emission (OES), and the like, such as to determine the film thickness, etch endpoint or etch uniformity (Col. 4, Line 40 through Col. 5, Line 45). In an embodiment, Davis teaches to perform etch trimming on a test substrate and determine a correlation between spectral position of minimum in spectrum of reflected radiation and width, then performing etching trimming on a product substrate while measuring in-situ the spectral position of minimum in spectrum of reflected radiation, and determine if the trimmed structure have the target width, then performing the etching trimming on other product substrates (Fig. 5A and 5B). Davis further teaches that if the trimmed structure does not have a target width, i.e. an outlier, then repeating the etching trimming and the in-situ measurement (Step 408 in Fig. 5B). It is noted that this reads on the claimed feature “executing a post-etching outlier model and determining to determine whether the product is an outlier” recited in claim 1. Davis fails to teach the claimed feature “receiving a wafer classification model that includes wafer types, product types and end-point detection (EPD) algorithms, wherein each EPD algorithm corresponds to a respective wafer type and a respective product type”. Coronel teaches a method of etching while monitoring for an end point (Claim 1), comprising- providing a product wafer having a layer to be etched 15 disposed over a substrate (Col. 1, Lines 32-63);- determining wavelengths to be used for the product from a product specification (Col. 9, Lines 24 through Col. 10, Line 17); - determining etch point criteria from the product specifications, comprising a theoretical computation model based on the product specifications and/or a previous experimentation on the product (Col. 10, Lines 18-53), wherein parameters STOP THICKNESS and RATE TIME (Col. 4, Lines 59-60; Col. 5, Lines 10-25) are determined for each wavelengths (Col. 10, Lines 53 through Col. 14, Line 20);- performing the etching on the product wafer while monitoring the etch process to detect an endpoint by analyzing the interference spectra of the reflected lights by using optical cables (abstract; Col. 8, Lines 25-66; Col. 14, Lines 21 through Col. 17, Line 37). In an embodiment, Coronel teaches that the etch endpoint criteria may be determined from a graph that is obtained through theoretical computation based on product specifications or by etching a product or sample wafer (Col. 10, Lines 19-24). Coronel further teaches that the above method advantageously enable etching a layer to a given thickness with great accuracy and a significant reduction in processing time while reducing rework due to a greater reproducibility (Col. 14, Lines 38-48). Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to use an etching model and wavelength for interferometric measurement based on a product specification and corresponding etch point criteria before and to monitor during the etching in the invention of Davis because Coronel teaches that this would advantageously enable etching a layer to a given thickness with great accuracy and a significant reduction in processing time while reducing rework due to a greater reproducibility. It is noted that the theoretical computation model based on the product specifications and/or a previous experimentation on the product that is used to determine the wavelengths for the measurement and to determine the end point criteria reads on the claimed wafer classification model that includes wafer types, product types and end-point detection (EPD) algorithms recited in claim 1.
--Claim 3: Although Davis fails to teach interpreting a lack of data for the product in the etching model as a faulty condition in the invention of Davis modified by Coronel, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to do so since Davis modified by Coronel teaches that the etching is based on the data from the etching model.--Claims 4, 6, 7, 8, 9, 10: It would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to perform an analysis to determine whether an optical instrument is faulty and the reason for the fault, and to determine a reason for a fault that is not caused by the optical instrument, such as due to a reference wafer.--Claim 12: Fig. 1B of Davis shows a structure is uncovered on the product wafer during the etching. --Claim 13: Davis modified by Coronel teaches to monitor the etching by using the etching model, as explained above.--Claim 16: It would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to stop the etching if the predicted end point time has been reached.--Claim 17: Coronel teaches to determine etch point criteria from product specifications, comprising a theoretical computation based on a previous experimentation on the product, as explained above--Claims 18, 19: Davis teaches that the ex-situ metrology comprises critical dimensions (CD), layer thickness, and the like; and the in-situ metrology comprises spectroscopy, interferometry, scatterometry, reflectometry, and the like, as explained above.
Claim 11 rejected under 35 U.S.C. 103 as being unpatentable over Davis in view of Coronel as applied to claim 7 above, and further in view of Choi et al. (U.S. PGPub. No. 20100332013), hereinafter “Choi”:--Claim 11: Davis modified by Coronel teaches the invention as in claim 7 above. Davis further teaches that the etch rate data may be determined by an OES monitor assembly (Col. 4, Line 52-59). Davis and Coronel fail to teach the claimed feature the etch rate model is based on voltage-current (VI) data. Choi teaches that etch rate may be determined by using OES and VI sensor ([0047]). Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to use an etch rate model based on OES data and VI data in the invention of Davis modified by Coronel because Choi teaches that this would be effective.
Claim 14 rejected under 35 U.S.C. 103 as being unpatentable over Davis in view of Coronel as applied to claim 12 above, and further in view of Lee et al. (U.S. Pat. No. 6475906), hereinafter “Lee”:--Claim 14: Davis modified by Coronel teaches the invention as in claim 12 above. Davis and Coronel fail to teach that the etching exposes a top of a transistor gate.Lee, also directed to fabricating a semiconductor device, teaches that the fabrication may comprise etching through a dielectric layer to expose a gate contact of a transistor by using endpoint detection (abstract; Fig. 8, Col. 5, Lines 14-21). Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to etch through a dielectric layer to expose a gate contact of a transistor by using endpoint detection in the invention of Davis modified by Coronel because Lee teaches that this is routinely performed in the art.
Response to Arguments
Applicant's arguments filed June 9, 2026 have been fully considered as follows:--Regarding Applicant’s argument that the previously cited prior arts fail to disclose the claimed feature “wafer classification model that includes wafer types, product types and end-point detection (EPD) algorithms” recited in claim 1, this argument is not persuasive. One of skill in the art would recognize that the theoretical computation model based on the product specifications and/or a previous experimentation on the product that is used to determine the wavelengths for the measurement and to determine the end point criteria taught by Davis modified by Coronel reads on this feature.--Regarding Applicant’s argument that the previously cited prior arts fail to disclose the claimed feature “during the etch process, running the EPD algorithm and determining an etching depth using data associated with the etching process measured by sensors, wherein an endpoint time of the etching process is determined by the etching depth or a maximum endpoint time” recited in claim 1, this argument is not persuasive. Davis modified by Coronel clearly teaches to determine the stop thickness and the etch duration for each wavelengths by using the theoretical computation model, then detect an endpoint by analyzing the interference spectra of the reflected lights by using optical cables.--Regarding Applicant’s argument that “the presently claimed subject matter performs the opposite operation, namely, executing a wafer classification model based on measured initial wafer data to determine a wafer type, a product type, and a corresponding EPD algorithm”, this argument is not commensurate with the scope of the claim. Claim 1 recites “receiving a wafer classification model that includes wafer types, product types and end-point detection (EPD) algorithms, wherein each EPD algorithm corresponds to a respective wafer type and a respective product type; receiving initial data of a wafer measured by an optical instrument; executing the wafer classification model based on the initial data; determining a wafer type, a product type, and an EPD algorithm for the wafer when
the wafer is classified by the wafer classification model, and determining that the wafer or the optical instrument is an outlier with respect to the wafer classification model when the wafer is not classified by the wafer classification model”. Thus claim 1 clearly recites an option in which the wafer is classified without using the EPD algorithm. In the current rejection, the wafer is measured and the measurements are processed through a model to see if it is an outlier.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP §706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS PHAM whose telephone number is (571) 270-7670 and fax number is (571) 270-8670. The examiner can normally be reached on MTWThF9to6 PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached on (571) 270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THOMAS T PHAM/Primary Examiner, Art Unit 1713
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