DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, Claims 14-20 (and newly added claims 21-33) in the reply filed on June 5, 2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 2, 2024 was considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14, 19-21, 24, and 29 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Jeng et al. (US 2022/0108967 A1) (“Jeng”), in view of MPEP 2131.01 references 1) Lasance, Clemens J.M., "The Thermal Conductivity of Silicon Dioxide", https://www.electronics-cooling.com/2004/08/the-thermal-conductivity-of-silicon-dioxide/, Aug. 1, 2004 (“Lasance”) and 2) Chowdhury et al., "Anisotropic Thermal Conductivity of Kapton Films, Composites, and Laminates", ACSAppl.Polym.Mater.2025,7,1440−1447 (“Chowdhury”).
Regarding claim 14, Jeng teaches at least in figures 1A-2:
forming a first heat-spreading substrate (120),
wherein the first heat-spreading substrate (120) comprises a substrate (120) and a conductive plug structure (128a-b/184),
the substrate (120) has a first surface (120a) and a second surface (120b),
the conductive plug structure (128a-b/184) has a first bonding pad portion (184), a second bonding pad portion (128a-b), and a via portion (There are a plurality of vias is 120),
the first bonding pad portion and the second bonding pad portion are respectively over the first surface and the second surface (as can be seen in figure 2 elements 184 and 128a-b are over different surfaces of the substrate 120);
bonding the first heat-spreading substrate (120) onto a first chip structure (elements in 230 above 120. This is also shown in figure 1G where elements in 160 are the same components.),
wherein a first thermal conductivity of the substrate is higher than a second thermal conductivity of the first chip structure (¶ 26, where 120 comprises silicon oxide, and ¶¶ 0054 and 83, where 160 comprises polyimide; Per Lasance the thermal conductivity of thermally grown silicon oxide is 1.3 W/mK; Per Chowdhury the thermal conductivity of polyimide is 0.2 W/mK, pg. 1440 at col. 2); and
bonding a second chip structure onto the first heat-spreading substrate (figure 2 shows a second chip structure area encompassing U2 on the opposite surface as the area encompassing U1),
wherein the second chip structure is electrically connected to the first chip structure through the conductive plug structure (The area encompassing including U1 and U2 are electrically connected through the via structure of 120),
the first thermal conductivity of the substrate is higher than a third thermal conductivity of the second chip structure (the second chip structure is the same as the first chip structure and thus, as shown above, has a lower thermal conductivity than the substrate), and
the first heat-spreading substrate contacts with the first chip structure and the second chip structure (120 so contacts).
Alternatively,
It would have been obvious that silicon oxide would have a higher thermal conductivity than polyimide based upon the prior art as the thermal conductivity of a material is an obvious characteristic, and/or inherent characteristic of said material as shown in Lasance and Chowdhury.
Regarding claim 19, Jeng teaches at least in figures 1A-2:
bonding a second heat-spreading substrate (320) onto the second chip structure (area which includes U2),
wherein a fourth thermal conductivity of the second heat-spreading substrate is higher than the third thermal conductivity of the second chip structure (the second heat-spearing substrate is the same as the first heating substrate and therefore the fourth thermal conductivity would be higher than the third conductivity for the reasons stated in claim 14.
Regarding claim 20, Jeng teaches at least in figures 1A-2:
forming a conductive bump on a surface of the first chip structure (290),
wherein the surface faces away the first heat-spreading substrate (the surfaces so faces).
Regarding claim 21, Jeng teaches at least in figures 1A-2:
wherein the substrate of the heat-spreading substrate (120) is made of a dielectric material (as stated in claim 14 120 is made of silicon oxide).
Regarding claim 24, Jeng teaches at least in figures 1A-2:
Claim 24 contains the same, and/or similar, limitations as claim 14 with the exception of: forming a conductive bump under the first chip structure.
Jeng teaches at least in figures 1A-2:
forming a conductive bump (380) under the first chip structure (area including U1).
Regarding claim 29, Jeng teaches at least in figures 1A-2:
providing a chip structure (230/U1) having a first surface (top of 230/U1) and a second surface opposite (bottom of 230/U1) to the first surface (top of 230/U1); and
bonding a first heat-spreading substrate (250) and a second heat-spreading substrate (120) onto the first surface (top of 230/U1) and the second surface (bottom of 230/U1) respectively,
wherein the first heat-spreading substrate (250) comprises a first substrate (121) and a first conductive plug structure (121a) passing through the first substrate (121),
the second heat-spreading substrate comprises a second substrate and a second conductive plug structure passing through the second substrate (250 is the same as 120 and would have the same structure as above),
a first thermal conductivity of the first substrate is higher than a second thermal conductivity of the chip structure, and a third thermal conductivity of the second substrate is higher than the second thermal conductivity of the chip structure (this is taught for the same reasons as claims 14 and 19 above).
Claim(s) 30-33 is/are rejected under 35 U.S.C. 103 as obvious over Jeng in view of MPEP 2131.01 references 1) Lasance and 2) Chowdhury.
Regarding claim 30, Jeng does not explicitly teach:
wherein the first substrate of the first heat-spreading substrate is thicker than the second substrate of the second heat-spreading substrate.
However, the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. Gardner v.TEC Syst., Inc., 725 F.2d 1338 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). MPEP 2144.04(IV)(A). Here there is nothing critical, nor are there any unexpected results arising. Therefore, the claimed device would not perform differently than the prior art device, and is thus, not patentably distinct.
Regarding claim 31, Jeng teaches at least in figures 1A-2:
wherein the first substrate of the first heat-spreading substrate and the second substrate of the second heat-spreading substrate are made of a same material (120 and 250 both formed of the same material).
Regarding claim 32, Jeng teaches at least in figures 1A-2:
wherein the first heat-spreading substrate (120 or 350) further comprises a first planarization layer (127; a planarization layer is considered a flat layer. 127 is shown as flat) over a third surface of the first substrate (top of figure 1A), and a fourth surface of the first planarization layer faces away from the first substrate and is more planar than the third surface of the first substrate (this is a relative measurement of planarization, i.e. flatness. This is a relative dimension rejected under the rational contained in MPEP 2144.04(IV)(A).
Regarding claim 33, Jeng teaches at least in figures 1A-2:
Claim 33 is considered a duplication of parts/layers. This mere duplication of parts/layers has no patentable significance as there are no new or unexpected results produced.
Allowable Subject Matter
Claims 15-18, 22-23, 25-28 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 15 and 25, the prior art does not teach:
the first chip structure and the second chip structure are bonded simultaneously.
Regarding claim 16, the prior art does not teach:
partially removing the substrate to form a through hole passing through the substrate; and
forming the conductive plug structure in the through hole and over the first surface and the second surface.
Conclusion
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/VINCENT WALL/Primary Examiner, Art Unit 2898
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