DETAILED ACTION
Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/02/2024 is filed after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objection
Claim 2 directs to a device, therefore “penetrates” directs to a method and not considered. Claim 2 should be amended to exclude the “method” limitation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8, 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen, U.S. Patent No. 11,437,415.
Regarding claim 1, Chen discloses: an electronic assembly comprising (Figs. 2-3):
a first package (Fig. 3) including a first electronic component 120 or 221 or 220 and a protection layer 230 covering the first electronic component, the protection layer 230 defining a cavity 16 (Fig. 3),
a second package 140/130 disposed over the cavity 16, and
a location-limiting element (either conductive layer 16, 131, or 132; Figs. 2-3) configured to fix the second package over the cavity (the conductive contact element is connected the first substrate to the second device 140/130 and thus considered as location-limiting element).
Regarding claim 2, Chen discloses wherein the cavity 16 is covered by the protection layer 230 (Figs. 2-3).
Regarding claim 8, Chen discloses: an electronic assembly comprising (Figs. 2-3):
a first package (Fig. 3) including a protection layer 230 having a cavity 16 (cavity covered by layer 230, Fig. 3),
a conductive element 132 disposed over the protection layer, and
a first location-limiting element (Fig. 3, the conductive contact in via 16, wherein the first location-limiting element is physically connected to a non-circuitry area of the conductive element).
Regarding claim 14, Chen discloses a second location-limiting element connected to the protection layer of the package and configured to fix the conductive element (the conductive material 13).
Regarding claim 15, Chen discloses the first and second location-limiting elements are disposed on opposite sides of the conductive element (the first conductive location-limiting element 16, the middle conductive material 132 or 131, the second conductive location limiting element 13).
Allowable Subject Matter
Claims 3-7, 9-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitations wherein the second package includes a second electronic component having an upper surface of a first dimension and a lateral surface of a second dimension longer than the first dimension, and wherein the upper surface of the second electronic component is substantially parallel to an upper surface of the protection layer (Claims 3-7), wherein the conductive element comprises: a first substrate having a lateral surface, and a first electronic component disposed adjacent to the lateral surface of the first substrate (Claims 9-13).
Claims 16-20 are allowed. The following is an examiner’s statement of reason for allowance: None of the references of record teaches or suggests the claimed having an electronic assembly comprising a first package including a protection layer having a cavity, and a second package disposed over the cavity and comprising: a carrier laterally electrical connected to the first package, and a second electronic component laterally electrically connected to the carrier.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/THAO P LE/Primary Examiner, Art Unit 2818