DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-13 in the reply filed on6/22/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, and 10-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2019/0041915, hereinafter, Park.)
In regard to claim 1, in figs. 8-11, Park discloses a display panel (para [0002]), comprising:
a base layer 100 (para [0034]);
a transistor T1 (para [0049]) disposed on the base layer and inherewntly including a semiconductor pattern and a gate G1, for example;
an organic layer disposed on the transistor (para [0031]);
a plurality of inorganic layers disposed between the transistor and the organic layer (paras [0031 and 0036]);
a first conductive pattern DL (para [0038]) disposed on any one of the inorganic layers; and
an organic light emitting element 300 (para [0049]) disposed on the organic layer,
wherein a first opening passing through at least one of the inorganic layers is defined, wherein the first opening does not overlap the first conductive pattern and the transistor on a plane, fig. 11.
Regarding claim 2, wherein the transistor is provided in plurality; and
the first opening is positioned between adjacent transistors of the plurality of transistors, fig. 11.
Regarding claim 3, Park further comprising: a plurality of pixel circuits, each of which includes the transistors; and
a second opening positioned between adjacent pixel circuits of the plurality of pixel circuits, Fig.5.
4. The display panel of claim 1, wherein the first opening comprises: a lower opening defined in a first inorganic layer of the inorganic layers; and an upper opening defined in a second inorganic layer disposed on the first inorganic layer of the inorganic layers, the upper opening being connected to the lower opening,
wherein the diameter of the upper opening is greater than or equal to the diameter of the lower opening.
Regarding claims 10-11, Park further comprising an organic material layer 141 (para [0126]) directly covering the first opening. Fig. 3.
Regarding claim 12, wherein the base layer comprises a folding region adjacent to a folding axis, and a non-folding region across the folding region from the folding axis,
wherein at least a portion of the first opening extends in a direction parallel to the folding axis. Figs. 1-3.
Regarding claim 13, Park further comprising a second conductive pattern 230 disposed on any one among the inorganic layers, and spaced apart from the first conductive pattern,
wherein the first opening is positioned between the first conductive pattern and the second conductive pattern. Fig. 3.
Allowable Subject Matter
Claims 5-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art does not show wherein one edge of the gate or one edge of the first conductive pattern is aligned with a wall of the upper opening. And the gate and the first conductive pattern are disposed on the same layer; and 15 one side of the gate and one side of the first conductive pattern is aligned with the wall of the upper opening. And wherein:
the transistor comprises a first transistor including a first semiconductor pattern, a first gate, and an upper electrode, and a second transistor disposed spaced apart from the first transistor and including a second semiconductor pattern and a second gate; and
the inorganic layers comprise first to sixth layers sequentially stacked on the base layer,
wherein the first semiconductor pattern is disposed on the first layer, the first gate is disposed on the second layer, the upper electrode is disposed on the third layer, 5 the second semiconductor pattern is disposed on the fourth layer, and the second gate is disposed on the fifth layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN W HA whose telephone number is (571)272-1707. The examiner can normally be reached M-T: 8:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached at (571)-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN W HA/Primary Examiner, Art Unit 2814
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