Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 011/23/2024 was before after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 14-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang et al, US 12417992 B2 .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Huang teaches:
A method for forming a semiconductor device structure, comprising:
providing a substrate (110), a first insulating layer (130,150,190), and a conductive pillar (184) over the substrate, wherein the conductive pillar (184) is embedded in the first insulating layer (130,150), and a top surface of the conductive pillar (184) is exposed by the first insulating layer; (figure 1g)
forming a second insulating layer (212) over the first insulating layer (130,150,190)) and the conductive pillar (184), wherein the second insulating layer has a hole (TH2) over the top surface of the conductive pillar (184); (figure 1L) and
forming a conductive via structure (240) in the hole (TH2) and a conductive line (250) over the conductive via structure (240) and the second insulating layer (212), wherein the conductive via structure (240) has a first strip shape (figure 1L-1) in a first top view of the conductive via structure, a width of the conductive via structure is greater than a length of the conductive via structure, (figure 1L-1)
and the conductive line (250) is in direct contact with the conductive via structure (240) and wider than the conductive via structure.(figure 1L-1)
2. The method for forming the semiconductor device structure as claimed in
claim 1, wherein the conductive pillar (184) has a second strip shape in a second top view of
the conductive pillar. (figure 1L-1)
3. The method for forming the semiconductor device structure as claimed in
claim 2, wherein a first long axis of the conductive via structure (240) is substantially parallel to a second long axis of the conductive pillar (184) in a third top view of the conductive via structure (240) and the conductive pillar (184). (figure 1l-1)
4. The method for forming the semiconductor device structure as claimed in
claim 1, wherein the conductive via structure (240) is wider than the conductive pillar (184). Figure 1L-1
14. A method for forming a semiconductor device structure, comprising:
providing a substrate (110), a first insulating layer (130,150,190), and a conductive pillar (184) over the substrate, wherein the conductive pillar (184) is embedded in the first insulating layer (130,150,190), and a
top surface of the conductive pillar (184) is exposed by the first insulating layer (130,150,190); Figure 1I
forming a second insulating layer (212) over the first insulating layer (103,150,190) and the conductive pillar (184), wherein the second insulating layer (212) has a hole (TH2) exposing the top surface of the conductive pillar, the hole has an inner wall, the inner wall has a upper portion and a lower portion, the lower portion is between the upper portion and the conductive pillar (184), Figure 1I
and the lower portion is steeper than the upper portion; and
forming a conductive via structure (240) in the hole and a conductive line (250) over the
conductive via structure and the second insulating layer. Figure 1L
15. The method for forming the semiconductor device structure as claimed in
claim 14, wherein the lower portion of the inner wall is substantially perpendicular to a
top surface of the conductive pillar. (figure 13C)
16. A semiconductor device structure, comprising:
a substrate (110);
a first insulating layer (130,150,190) over the substrate;
a conductive pillar (184) over the substrate and embedded in the first insulating layer (130,150,190); Figure 1G
a second insulating layer (212) over the first insulating layer and the conductive pillar (184); Figure 1I
a conductive via structure (240) passing through the second insulating layer (212) and
connected to the conductive pillar (184), wherein the conductive via structure has a first strip shape in a first top view of the conductive via structure; (figure 1L-1) and
a conductive line (250) over the conductive via structure (240) and the second insulating layer (212). Figure 1L
17. The semiconductor device structure as claimed in claim 16, wherein the
conductive line has a second strip shape, and a first long axis of the conductive via
structure is substantially parallel to a second long axis of the conductive line in a second
top view of the conductive via structure and the conductive line. Figures 1L and 1L-1
18. The semiconductor device structure as claimed in claim 16, wherein the
conductive pillar has a second strip shape in a second top view of the conductive pillar. Figure 1L-1
19. The semiconductor device structure as claimed in claim 16, wherein the
conductive via structure is wider than the conductive pillar. Figure 1L-1
20. The semiconductor device structure as claimed in claim 19, wherein the
conductive pillar extends into the conductive via structure. Figure 1L
15. The method for forming the semiconductor device structure as claimed in
claim 14, wherein the lower portion of the inner wall is substantially perpendicular to a
top surface of the conductive pillar.
Allowable Subject Matter
Claim 5-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art references fail to teach:
5. The method for forming the semiconductor device structure as claimed in
claim 4, wherein the hole of the second insulating layer exposes a sidewall of the
conductive pillar.
Conclusion
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/Primary Examiner, Art Unit 2893
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