DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-14 and 21-26 are pending.
Claims 1 and 7 are amended.
Claims 15-20 are cancelled.
Claims 21-26 are new.
Election/Restrictions
Applicant’s election without traverse of Inventions I and II, corresponding to claims 1-14, in the reply filed on 06/22/2026 is acknowledged.
Claims 15-20 have been cancelled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention III. Election was made without traverse in the reply filed on 06/22/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/03/2024 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
FIN-FET DEVICE HAVING AN INTERMEDIATE DIELECTRIC LAYER FOR FIN UNIFORMITY
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically, it is unclear in claim 14 how removing the dummy gate structure to expose the dielectric layer and the first to fourth semiconductor layers in the semiconductor fin can occur when claim 9 specifies that the fourth semiconductor layer is etched away to leave an opening and the dielectric is formed in that opening. It is unclear how removing the dummy gate structure can expose the dielectric layer and the fourth semiconductor layer if that fourth semiconductor layer was removed in order to deposit the dielectric layer. For the purposes of examination, it will be interpreted that claim 14 was intended to read “removing the dummy gate structure to expose the dielectric layer and the first to third semiconductor layers in the semiconductor fin,” support for which can be found in at least Fig. 13.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-14, and 21-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chan et al. (US PGPub 2023/0197726; herein known as Chan).
Regarding claim 1, Chan teaches (Figs. 1A-1N) a method for manufacturing an integrated circuit device, comprising: depositing an epitaxial stack ([0100]) over a semiconductor substrate (128, [0094]), wherein the epitaxial stack comprises a plurality of first (138, [0098]) and second (136, [0098]) semiconductor layers alternatively arranged over the semiconductor substrate and a third semiconductor layer (134, [0097]) over the first and second semiconductor layers; patterning the epitaxial stack to form a semiconductor fin (140, [0096]); forming a dummy gate structure (146, [0095]) over the semiconductor fin; replacing the third semiconductor layer in the semiconductor fin with a dielectric layer (154, [0112]); and replacing the dummy gate structure and the first semiconductor layers in the semiconductor fin with a metal gate structure (174, 168, [0122, 0126]).
Regarding claim 2, Chan teaches (Figs. 1A-1N) the method of claim 1, wherein a germanium concentration of the third semiconductor layer (134, [0101]) is greater than a germanium concentration of the first semiconductor layers ([0101]), and the germanium concentration of the first semiconductor layers (138, [0101]) is greater than a germanium concentration of the second semiconductor layers (136, [0102]).
Regarding claim 3, Chan teaches (Figs. 1A-1N) the method of claim 1, further comprising: etching a source/drain recess (144, [0110]) in the semiconductor fin prior to replacing the third semiconductor layer in the semiconductor fin with the dielectric layer ([0110]); and forming a source/drain epitaxial structure (156, 162 [0115]) in the source/drain recess after replacing the third semiconductor layer in the semiconductor fin with the dielectric layer ([0112]).
Regarding claim 5, Chan teaches (Figs. 1A-1N) the method of claim 1, further comprising: forming a plurality of inner spacers (115, [0188]) on opposite sides of the first semiconductor layers after replacing the third semiconductor layer ([0112]) in the semiconductor fin with the dielectric layer.
Regarding claim 6, Chan teaches (Figs. 1A-1N) the method of claim 1, wherein the metal gate structure (174, 168, [0126]) wraps the dielectric layer and the second semiconductor layers (see Fig. 1N).
Regarding claim 7, Chan teaches (Figs. 1A-1N) the method of claim 1, wherein replacing the third semiconductor layer (134, [0097]) in the semiconductor fin with the dielectric layer (154, [0112]) comprises: etching the third semiconductor layer ([0112]) to leave an opening (152, [0112]) between the dummy gate structure (146, [0095]) and a topmost one of the first semiconductor layers (138a, [0112]); and depositing a dielectric material (154, [0112]) into the opening between the dummy gate structure and the topmost one of the first semiconductor layers (see Fig. 1E-1F).
Regarding claim 8, Chan teaches (Figs. 1A-1N) the method of claim 1, wherein a thickness of the third semiconductor layer (134, [0104]) is different from a thickness of the first semiconductor layers (138, [0104]).
Regarding claim 9, Chan teaches (Figs. 1A-1N) a method for manufacturing an integrated circuit device, comprising: depositing an epitaxial stack ([0100]) over a semiconductor substrate (128, [0094]), wherein the epitaxial stack comprises a first semiconductor layer (136b, [0104]), a second semiconductor layer (138a, []) over the first semiconductor layer, a third semiconductor layer (136a, [0104]) over the second semiconductor layer, and a fourth semiconductor layer (134, [0104]) over the third semiconductor layer; patterning the epitaxial stack to form a semiconductor fin (140, [0096]); forming a dummy gate structure (146, [0095]) over the semiconductor fin; etching a source/drain recess (144, [0110]) in the semiconductor fin to expose sidewalls of the first to fourth semiconductor layers in the semiconductor fin; etching away the fourth semiconductor layer to leave an opening (152, [0112]) between the dummy gate structure and the third semiconductor layer; forming a dielectric layer (154, [0112]) in the opening between the dummy gate structure and the third semiconductor layer; and forming a source/drain epitaxial structure (152, 162, [0112]) in the source/drain recess after forming the dielectric layer.
Regarding claim 10, Chan teaches (Figs. 1A-1N) the method of claim 9, further comprising: laterally recessing the sidewalls of the first and third semiconductor layers after forming the dielectric layer (Fig. 1H, [0118]); and forming a plurality of inner spacers (115, [0118]) on the recessed sidewalls of the first and third semiconductor layers (136a, b, [0118]).
Regarding claim 11, Chan teaches (Figs. 1A-1N) the method of claim 9, wherein forming the dielectric layer (154, [0112]) is performed such that the sidewalls of the first to third semiconductor layers (136a,b, [0118]) are exposed in the source/drain recess (Fig. 1G).
Regarding claim 12, Chan teaches (Figs. 1A-1N) the method of claim 9, wherein the dummy gate structure comprises a dummy gate dielectric layer (not shown, [0051]) and a dummy gate electrode (110, [0105]), and a top surface of the dielectric layer is in contact with the dummy gate dielectric layer ([0051]).
Regarding claim 13, Chan teaches (Figs. 1A-1N) the method of claim 9, wherein a bottom surface of the dielectric layer (154, [0112]) is in contact with the third semiconductor layer (136a, [0112]).
Regarding claim 14, Chan teaches (Figs. 1A-1N) the method of claim 9, further comprising: removing the dummy gate structure to expose the dielectric layer ([0119]) and the first to fourth semiconductor layers in the semiconductor fin; and replacing the first and third semiconductor layers with a metal gate structure ([0121]).
Regarding claim 21, Chan teaches (Figs. 1A-1N) a method for manufacturing an integrated circuit device, comprising: forming a plurality of channel layers (138, [0104]) over a semiconductor substrate (128, [0094]), the plurality of channel layers being vertically spaced apart from each other (see Fig.); forming an epitaxial layer (134, [0104]) over the plurality of channel layers; etching recesses (144, [0110]) extending through the plurality of channel layers and the epitaxial layer; after etching the recesses, replacing the epitaxial layer with a dielectric layer (154, [0112]); forming source/drain epitaxial structures (156, 162 [0115]) in the recesses; and forming a gate structure (174, 168, [0126]) extending across the plurality of channel layers and the dielectric layer.
Regarding claim 22, Chan teaches (annotated Fig. 1N below) the method of claim 21, wherein the gate structure has a first portion (FP, [0127]) vertically between the plurality of channel layers (138, [0131]), a second portion (SP, [0129]) vertically between the dielectric layer and a topmost one of the channel layers, and a third portion (ThP, [0126]) over the dielectric layer (154, [0112]).
PNG
media_image1.png
606
716
media_image1.png
Greyscale
Regarding claim 23, Chan teaches (Figs. 1A-1N) the method of claim 22, wherein a bottom surface of the dielectric layer is in contact with the second portion (166, [0129]) of the gate structure, and a top surface of the dielectric layer is in contact with the third portion (174, [0126]) of the gate structure (See Fig. 1N).
Regarding claim 24, Chan teaches (Figs. 1A-1N) the method of claim 22, further comprising: forming gate spacers (114, [0108]) prior to etching the recesses extending through the plurality of channel layers and the epitaxial layer (Fig. 1B), wherein the gate spacers are on opposite sides of the third portion of the gate structure (ThP, annotated Fig. 1N above), wherein the gate spacers are in contact with the dielectric layer (154, [0112]).
Regarding claim 25, Chan teaches (Figs. 1A-1N) the method of claim 22, wherein a width of the third portion (ThP) of the gate structure is less than a width of the first portion (FP) of the gate structure. See annotated Fig. 1N, above.
Regarding claim 26, Chan teaches (Figs. 1A-1N) the method of claim 21, wherein the gate structure comprises interfacial dielectric layers (166, [0121]) in contact with the plurality of channel layers, and a high-k dielectric layer ([0121]) over the interfacial dielectric layer and in contact with the dielectric layers (interfacial layer is interpreted as the face along with the gate dielectric contacts adjacent channel layers).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chan as applied to claim 3 above.
Regarding claim 4, Chan teaches the method of claim 3, wherein a top surface of the source/drain epitaxial structure (156, 162, [0127]) is above a top surface of a topmost one of the second semiconductor layers (138a, [0126]), but does not explicitly teach wherein it is lower than a top surface of the dielectric layer.
The instant application does not provide for criticality of the claimed feature wherein the top surface of the source/drain epitaxial structure is lower than a top surface of the dielectric layer, only denoting that it “can be lower than a top surface of the dielectric layer.”
Chan teaches wherein the source/drain material can be etched back to define source/drain electrodes with a desired height ([0127]), for the purpose of providing electrical contact from source and drain bodies to the device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chan to include wherein a top surface of the source/drain epitaxial structure is lower than a top surface of the dielectric layer for the predictable result of providing electrical contact from source and drain bodies to the device. See MPEP 2143.I(B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights