DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 11, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Morikawa et al. US 2018/0026127 A1 in view of Banerjee et al. US 2018/0175188 A1. Morikawa discloses (see, for example, FIG. 4, and 5A) a semiconductor device comprising a semiconductor layer structure 101/102 comprising a drift region 102, plurality of channel regions 201a, plurality of JFET regions 204. In FIG. 4, Morikawa discloses the plurality of channel regions 201a having a ring-shaped channel region that has a ring shape and surrounds a respective one of the JFET regions 204 when viewed in plan view. In paragraph [0066], Morikawa discloses the drift region being n-type (i.e. first conductivity type) SiC; in paragraph [0067], discloses the plurality of channel regions 201a being p-type (i.e. second conductivity type); and in paragraph [0069], discloses the plurality of JFET regions 204 being n-type (i.e. first conductivity type). Morikawa does not disclose each channel region comprising a ring-shaped channel region that has a hexagonal ring shape, and wherein each of the JFET regions has a hexagonal shape when viewed in plan view. However, Banerjee discloses (see, for example, FIG. 7) a semiconductor device comprising a channel region comprising a ring-shaped channel region that has a hexagonal ring shape that surrounds JFET regions that also have a hexagonal shape when viewed in plan view. It would have been obvious to one of ordinary skill in the art, at a time of prior to the effective filing date, to have each channel region comprising a ring-shaped channel region that has a hexagonal ring shape, and wherein each of the JFET regions has a hexagonal shape when viewed in plan view in order to increase channel width, and therefore improve overall packing density; furthermore, such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 2, see, for example, FIG. 4 wherein Morikawa discloses the
ring-shaped channel regions 201a/201b being arranged as a plurality of columns of ring-shaped channel regions when viewed in plan view.
Regarding claim 11, see, for example, FIG. 5A wherein Morikawa discloses (see, for example, FIG. 5A) a semiconductor device comprising channel regions 201a on a well region 201, and in FIG. 4, discloses the JFET region 204 within openings in the well region 201.
Regarding claim 16, see, for example, FIG. 5A wherein Morikawa discloses a continuous gate electrode 222 that extends throughout an active region of the semiconductor device.
Allowable Subject Matter
Claims 20, 27, 28, and 48 thru 52 are allowed. The references of record, either singularly or in combination, do not teach or suggest at least a semiconductor device, comprising a semiconductor layer structure comprising a source region having the first conductivity type, where the channel regions are in between the drift region and the source region, and the semiconductor layer structure comprises a plurality of spaced-apart first openings that extend along a first axis and a plurality of spaced-apart second openings that extend along a second axis that is parallel to the first axis; where the first gate electrode includes first downward protrusions that extend into the respective first openings and the second gate electrode includes first downward protrusions that extend into the respective second openings, wherein a first sub-set of ring-shaped channel region surround respective ones of the first downward protrusions and a second sub-set of ring-shaped channel region surround respective ones of the second downward protrusions.
Regarding claims 48-52, the references of record, either singularly or in combination, do
not teach or suggest at least a semiconductor device, comprising: a semiconductor layer structure comprising a plurality of JFET regions having the first conductivity type that are arranged in a plurality of columns that extend in parallel along respective first axes and are arranged in a plurality of rows that extend in parallel along respective second axes that extend perpendicular to the first axes, and a plurality of well contact regions having the second conductivity type that are spaced-apart from each other, each well contact region having a higher second conductivity type doping concentration than the well region, wherein adjacent JFET regions in each row are in adjacent ones of the plurality of columns; a first gate electrode that extends on an upper surface of the semiconductor layer structure above a first of the columns of JFET regions; a second gate electrode that extends on an upper surface of the semiconductor layer structure above a second of the columns of the JFET regions; and a source metallization on the semiconductor layer structure, the source metallization having a downwardly protruding region that extends in between the first gate electrode and the second gate electrode and in parallel to both the first gate electrode and the second gate electrode, the downwardly protruding region directly contacting multiple of the well contact regions in the plurality of well contact region.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 2, 11, 16, 20, 27, 28, and 48-52 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Eugene Lee
October 6, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
