DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “wherein top surfaces of the first and the second metal lines are substantially coplanar,” of claim 13 and, “wherein top surfaces of the bottom metal lines of the gate path metal lines and the thermal path metal lines are substantially coplanar,” of claim 20 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (US PGPub 20240429226 A1; hereinafter referred to as "Zhou”) in view of Paul et al. (US PGPub 20200027898 A1; hereinafter referred to as "Paul”) and Or-Bach et al. (US PGPub 20180197812 A1; hereinafter referred to as "Or-Bach”).
Re claim 1: Paul teaches a semiconductor structure, comprising: a device layer (annotated FIG. 7B: el. device layer; para. 73|devices formed in a device layer, provided between the buried oxide (BOX) layer and the superstructure layer of FIG. 7B) having a transistor device (FIG. 7B: el. 701; para. 75), the transistor device includes a channel region between source/drain (S/D) regions (FIG. 7B: el. B, S (604), D (606); para. 73) and a gate stack over the channel region (FIG. 7B: el. 608, B; para. 73); a frontside interconnect structure over a frontside of the device layer (FIG. 7B: el. superstructure, 708; para. 77, abstract, 12), the frontside interconnect structure includes thermal path metal features (FIG. 7B: el. 702, 708, 440; para. 76-77, 72); a bonding oxide layer (FIG. 7B: el. 1st passivation layer; para. 18) over the frontside interconnect structure (FIG. 7B), the bonding oxide layer embeds a thermal path metal contact (FIG. 7B: el. 502; para. 77, 69-71) electrically connected to the thermal path metal features (FIG. 7B: el. 502, (702, 708, 440); para. 77, 69-71); and a carrier substrate (FIG. 7B: el. Handle Wafer; para. 18) over the bonding oxide layer (FIG. 7B: el. Handle Wafer, 1st passivation layer), the carrier substrate landing on a top surface of the thermal path metal contact (FIG. 7B: el. Handle Wafer, 502). Paul fails to teach a device layer having a transistor device and a PN junction structure coupled to the transistor device, the PN junction structure includes a first doped region and a second doped region, and the first doped region is electrically connected to the gate stack, and fails to teach the thermal path metal features electrically connected to the second doped region of the PN junction structure.
In a similar field of endeavor, Zhou teaches a device layer having a transistor device (FIG. 2: el. 204; para. 61) and a PN junction structure (FIG. 2: el. 202; para. 61) coupled to the transistor device (FIG. 2: el. 204, 202; para. 61-62), the transistor device includes a channel region between source/drain (S/D) regions (FIG. 3-1: el. 300-2; para. 65| silicon channels 304-2 formed in the channel region of the field-effect transistor 300-2) and a gate stack over the channel region (FIG. 3-1: el. 300-2; para. 65|gate stack, PC, of FET 300-2 formed over the channel region), the PN junction structure includes a first doped region (FIG. 2: el. 206 P+; para. 61) and a second doped region (FIG. 2: el. 206 N+; para. 61), and the first doped region is electrically connected to the gate stack (FIG. 2: 206 P+, M1, PC of 204; para. 61-62). Zhou also teaches a benefit of incorporating a PN junction reverse-biased diode electrically connected to the gate stack of a transistor in the device layer is protection of the gate oxide of the transistor from ESD or plasma damage by providing a current release path, such as for charges built up during back-end-of-line processing (para. 62). Paul teaches the thermal metal path features electrically connected to dummy gate structures to provide a thermal path for heat produced by the transistor (Paul – para. abstract, 72), but both Paul and Zhou fail to teach the thermal path metal features electrically connected to the second doped region of the PN junction structure (the side of the PN junction diode structure not already electrically connected to the gate stack).
In a similar field of endeavor, Or-Bach teaches a thermal path including a reverse-biased diode connected to a portion of a transistor so that the thermal path may conduct heat but not conduct current or electric signal (para. 74: sent. 6), and teaches a benefit of a thermal path connected to transistor structures is to keep the transistor within desirable temperature limits (para. 74: sent. 5). Or-Bach teaches thermal paths connected to reverse diodes which are connected to transistor structures (para. 74: sent. 5), and Or-Bach in combination with Paul and Zhou teaches thermal path metal features electrically connected to the second doped region of the PN junction structure (Or-Bach - para. 74: sent. 5).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Paul with the teachings of Zhou and the teachings of Or-Bach, to enable using reverse-biased PN junction diode of Zhou and the connectivity of a reverse-biased PN junction diode to a transistor and a thermal path of Or-Bach, for the benefit of protecting the transistor by keeping the transistor within desirable temperature limits and providing a current release path to mitigate ESD or plasma induced damage.
Re claim 2: The combination of Paul, Zhou, and Or-Bach teaches the semiconductor structure of claim 1, wherein the carrier substrate is of a semiconductor material (Paul – FIG. 7B: el. Handle Wafer (e.g., Si); para. 18).
Re claim 3: The combination of Paul, Zhou, and Or-Bach teaches the semiconductor structure of claim 1, wherein the thermal path metal features include metal lines (Paul - FIG. 7B: el. 702) vertically disposed between metal vias (Paul - FIG. 7B: el. 708, 440), and the frontside interconnect structure further includes an intermetal dielectric (IMD) layer embedding the metal lines and metal vias (Paul - FIG. 7B: el. superstructure (e.g., interconnects, passivation, contacts, etc.); para. 77).
Re claim 4: The combination of Paul, Zhou, and Or-Bach teaches the semiconductor structure of claim 1, wherein the frontside interconnect structure further includes frontside gate metal features electrically connected to the gate stack (Zhou – FIG. 2: el. M1; para. 61).
Re claim 7: The combination of Paul, Zhou, and Or-Bach teaches the semiconductor structure of claim 1, wherein the first doped region is adjacent the second doped region (Zhou - FIG. 2: el. 206 P+, 206 N+), the first doped region is doped with a first type dopant (Zhou - FIG. 2: el. 206 P+; para. 61, 51), the second doped region is doped with a second type dopant (Zhou - FIG. 2: el. 206 N+; para. 61, 51) opposite the first type dopant.
Re claim 9: The combination of Paul, Zhou, and Or-Bach teaches the semiconductor structure of claim 7, wherein the S/D regions of the transistor device are doped with a p-type dopant (Zhou - para. 50, 48), wherein the first doped region is doped with a p-type dopant (Zhou - FIG. 2: el. 206 P+; para. 61, 51), and the second doped region is doped with an n-type dopant (Zhou - FIG. 2: el. 206 N+; para. 61, 51).
Allowable Subject Matter
Claims 5-6, 8, and 10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 5: The closest prior art, Zhou ‘226, Paul ‘898, and Or-Bach ‘812, either alone or in combination fails to disclose or suggest, “wherein the device layer further includes another transistor device, further comprising: a backside interconnect structure over a backside of the device layer, wherein the backside interconnect structure includes backside metal features electrically connected to an S/D region of the another transistor device, wherein the S/D region of the another transistor device is electrically connected to the gate stack through frontside gate metal features in the frontside interconnect structure,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 6: The closest prior art, Zhou ‘226, Paul ‘898, and Or-Bach ‘812, either alone or in combination fails to disclose or suggest, “wherein the device layer further includes another transistor device, further comprising: a backside interconnect structure over a backside of the device layer, wherein the backside interconnect structure includes backside metal features electrically connected to an S/D region of the another transistor device, wherein the S/D region of the another transistor device is electrically connected to the gate stack through frontside gate metal features in the frontside interconnect structure,” of claim 5 on which claim 6 depends, in combination with the additionally claimed features, as claimed by the applicant.
Re claim 8: The closest prior art, Zhou ‘226, Paul ‘898, and Or-Bach ‘812, either alone or in combination fails to disclose or suggest, “wherein the S/D regions of the transistor device are doped with an n-type dopant, wherein the first doped region is doped with an n-type dopant, and the second doped region is doped with a p-type dopant,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 10: The closest prior art, Zhou ‘226, Paul ‘898, and Or-Bach ‘812, either alone or in combination fails to disclose or suggest, “wherein the device layer further includes a second transistor device and a second PN junction structure coupled to the second transistor device, the second transistor device includes a second channel region between second S/D regions and a second gate stack over the second channel region, the second PN junction structure includes a third doped region and a fourth doped region, and the third doped region is electrically connected to a gate electrode of the second gate stack, wherein the frontside interconnect structure further includes second thermal path metal features electrically connected to the fourth doped region of the second PN junction structure, wherein the bonding oxide layer embeds a second thermal path metal contact electrically connected to the second thermal path metal features, wherein the carrier substrate lands on a top surface of the second thermal path metal contact,” in combination with the additionally claimed features, as claimed by the applicant.
Claims 11-20 are allowed.
The following is an examiner’s statement of reasons for allowance. Allowable subject matter has been indicated because the closest prior art references of record, Zhou et al. (US PGPub 20240429226 A1), Paul et al. (US PGPub 20200027898 A1), and Or-Bach et al. (US PGPub 20180197812 A1), either alone or in combination fails to disclose or suggest:
“a semiconductor structure, comprising: transistor devices having channel regions between source/drain (S/D) regions and gate stacks over the channel regions; PN junction structures having first doped regions and second doped regions oppositely doped from the first doped regions, and the first doped regions are electrically connected to the gate stacks; thermal path metal features over the PN junction structures and electrically connected to the second doped regions of the PN junction structure; and a carrier substrate over the thermal path metal features and in metal contact with the thermal path metal features,”
or, “a semiconductor structure, comprising: transistor devices in a device layer, each transistor device having a channel region between source/drain (S/D) regions and a gate stack over the channel region; PN junction structures in the device layer, each PN junction structure having a first doped region and a second doped region oppositely doped from the first doped region, the first doped region is electrically connected to one of the gate stacks; and a frontside interconnect structure over the device layer, the frontside interconnect structure includes gate path metal lines electrically connected to the gate stacks and thermal path metal lines electrically connected to the second doped regions of the PN junction structures”.
The prior art references of record do not explicitly teach or render obvious, a semiconductor structure comprising a plurality of PN junction structures having first doped regions connected to a plurality of gate stacks of a plurality of transistor structures, in combination with the additionally claimed features, as claimed by the applicant.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
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/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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