Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2, Claims 1, 3, 4, 7-14 and 17-20 in the reply filed on 04/14/2026 is acknowledged. However, the office notes that claims 3-4 are dependent on non-elected claim 2. Therefore, claims 2-6 and 15-16 are withdrawn. Claims 1, 7-14 and 17-20 are examined below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7-9, 14 and 20 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Cai (US 20170069616 A1).
Re: Independent Claim 1, Cai discloses a structure comprising:
a vertical silicon controlled rectifier (Fig. 5 and ¶ [0051], SCR 90); and
a triggering device adjacent to the vertical silicon controlled rectifier (Fig. 5 and ¶ [0051], Triggering MOS transistor 54 is adjacent to SCR 90),
the triggering device and the vertical silicon controlled rectifier sharing a diffusion region within a semiconductor substrate (Fig. 5, N+ region 40 are formed in P-sub 64 and are connected to cathode K of the vertical SCR 90. Triggering MOS transistor 54 is formed between N+ regions 40 and 44. Thus the same N+ diffusion region 40 within P-substrate 64 is shared by the vertical SCR 90 and triggering MOS transistor 54).
Re: Claim 7, Cai discloses all the limitations of claim 1 on which this claim depends.
Cai further discloses,
wherein the vertical silicon controlled rectifier comprises an NPNP device (Cai teaches, in ¶ [0083], P and N wells could be reversed, and a NPNP vertical SCR used rather than a PNPN vertical SCR. Thus, Cai discloses a dopant reversed version SCR 90 in which the vertical SCR comprises an NPNP device) and
the triggering device comprises an PMOS transistor (Cai teaches, in ¶ [0084], triggering MOS transistor 54 may be implemented as a p-channel transistor rather than an n-channel transistor. A p-channel MOS transistor corresponds to a PMOS transistor).
Re: Claim 8, Cai discloses all the limitations of claim 7 on which this claim depends.
Cai further discloses,
wherein the PMOS transistor is a lateral PMOS transistor (Cai teaches, in ¶ [0034], a lateral MOS transistor is formed where 40 and 44 act as source/drain regions. Because Cai teaches that this same triggering MOS transistor 54 may be implemented as a p-channel transistor (as explained for claim 7 above), Cai discloses the claimed lateral PMOS transistor).
Re: Claim 9, Cai discloses all the limitations of claim 8 on which this claim depends.
Cai further discloses,
wherein the shared diffusion region comprises a P+ source region of the PMOS transistor and a P+ contact of the NPNP device (Cia discloses, in Fig. 5 and ¶ [0034], that source/drain regions 40 and 44 act as source/drain regions of triggering MOS transistor 54, and that regions 40 are also final terminal of the SCR structure 90. In the dopant-reversed NPNP/PMOS embodiment taught by Cia, in ¶ [0083], the region corresponding to N+ region 40 in the illustrated PNPN/NMOS embodiment of Fig. 5 is a P+ region. Therefore, the dopant-reversed region 40 comprises a P+ source region of the PMOS transistor 54 and also a P+ contact/final terminal of the NPNP vertical SCR 90).
Re: Independent Claim 14, Cai discloses A structure comprising:
a vertical silicon controlled rectifier (Fig. 5 and ¶ [0051], SCR 90) comprising a diffusion region in a semiconductor substrate of a first dopant type (Fig. 5, N+ region 40 are formed in P-sub 64 and are connected to cathode K of the vertical SCR 90. Thus, N+ region 40 constitute diffusion regions of a first dopant type within semiconductor substrate 64 and form part of the vertical SCR 90);
a lateral triggering device sharing the diffusion region with the vertical silicon controlled rectifier (Fig. 5, triggering MOS transistor 54 is formed between N+ regions 40 and 44. Thus the same N+ diffusion region 40 within P-substrate 64 is shared by the vertical SCR 90 and triggering MOS transistor 54. Regarding the triggering MOD transistor being the claimed “lateral triggering device”, Cai teaches, in ¶ [0034], a lateral MOS transistor is formed where 40 and 44 act as source/drain regions. Because Cai teaches that this same triggering MOS transistor 54 may be implemented as a p-channel transistor (as explained for claim 7 above), Cai discloses the claimed lateral triggering device/transistor), the diffusion region being a source region for the lateral triggering device (Cia teaches, in Fig. 9c and ¶ [0062], triggering MOS transistor 54 is formed between N+ regions 40 and 44, and that the current flows from N+ region 44 to N+ region 40. Cai, in ¶ [0063], further refers to N+ region 40 as being at the lower source voltage of triggering MOS transistor 54. Thus, in Cai’s NMOS triggering transistor embodiment, N+ region 40 functions as a source region of the triggering MOS transistor 54); and
a body contact of a second dopant type connecting to ground and tied to the semiconductor substrate (Cai teaches, in Figs. 2 and 5 and ¶ [0036], P +taps 66 that allow P-substrate 64 to be biased, such as to ground. The P+ taps 66 are of second dopant type opposite the N+ diffusion/source region 40 and are tied to P-substrate 64 to provide the substrate/body bias).
Re: Independent Claim 20, Cai discloses a method comprising:
forming a vertical silicon controlled rectifier (Fig. 5 and ¶ [0051], SCR 90); and
forming a triggering device adjacent to the vertical silicon controlled rectifier (Fig. 5 and ¶ [0051], forming triggering MOS transistor 54 is adjacent to SCR 90),
the triggering device and the vertical silicon controlled rectifier sharing a diffusion region within a semiconductor substrate (Fig. 5, N+ region 40 are formed in P-sub 64 and are connected to cathode K of the vertical SCR 90. Triggering MOS transistor 54 is formed between N+ regions 40 and 44. Thus the same N+ diffusion region 40 within P-substrate 64 is shared by the vertical SCR 90 and triggering MOS transistor 54).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cai (US 20170069616 A1).
Re: Claim 12, Cai discloses all the limitations of claim 7 on which this claim depends.
Regarding the limitation “further comprising an N+ body contact connecting to ground and tied to an n-well in the semiconductor substrate”, Cai discloses, in Figs. 2 and 5 and ¶ [0036], a P+ taps 66 that allows P-substrate 64 to be biased, such as to ground. Cai further disclosed that the triggering MOS transistor 54 is formed using regions 40 and 44 over the substrate/body 64. Thus, Cai teaches providing a body contact/tap for biasing the body region of the triggering MOS transistor. Although Cai’s illustrated embodiment uses P+ taps 66 tied to P-substrate 64, Cai expressly teaches the dopant-reversed embodiment, in ¶ [0083], in which P and N wells are reversed and triggering MOS transistor 54 is implemented as a p-channel transistor. In such a dopant-reversed PMOS embodiment, the body region of the PMOS transistor is an n-type well/body region 64, and the corresponding body tap/contact 66 would be an N+ contact tied to the n-type well/body region.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide the dopant-reversed PMOS embodiment of Cai with an N+ body contact tied to the n-well and connected to ground in order to provide a defined body potential and reduce unwanted parasitic effect in the ESD protection structure.
Re: Claim 17, Cai discloses all the limitations of claim 14 on which this claim depends.
wherein the vertical silicon controlled rectifier comprises a NPNP device (Cai teaches, in ¶ [0083], P and N wells could be reversed, and a NPNP vertical SCR used rather than a PNPN vertical SCR. Thus, Cai discloses a dopant reversed version SCR 90 in which the vertical SCR comprises an NPNP device) and the triggering device comprises an PMOS transistor (Cai teaches, in ¶ [0084], triggering MOS transistor 54 may be implemented as a p-channel transistor rather than an n-channel transistor. A p-channel MOS transistor corresponds to a PMOS transistor), the diffusion region comprises a P+ diffusion region (In Fig. 5, Cai’s PNPN/NMOS embodiment, N+ region 40 is the diffusion region. In the dopant-reversed NPNP/PMOS embodiment expressly taught by Cai in ¶ [0084], the corresponding diffusion region 40 would be a P+ diffusion region) and the body contact comprising an N+ body contact tied to an n-well in the semiconductor substrate (Cai teaches P+ taps 66 tied to P-substrate 64 and connected to ground in the PNPN/NMOS embodiment of Fig. 5. In the dopant-reversed NPNP/PMOS embodiment expressly suggested by Cai, the corresponding substrate/body region for the PMOS triggering transistor would be an n-type well/body region, and the corresponding body contact would be an N+ body contact tied to the n-well and connected to ground).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Cai’s disclosed vertical SCR and triggering MOS transistor arrangement using reverse conductivity types expressly suggested by Cai, including and NPNP vertical SCR, a PMOS triggering transistor, a P+ shared source/contact diffusion region, and an N+ grounded body contact tied to the n-well in order to produce the complementary structure as required while preserving the same SCR-triggering operation.
Claims 10, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cai (US 20170069616 A1) in view of Campi (US 20120126285 A1).
Re: Claim 10, Cai discloses all the limitations of claim 9 on which this claim depends.
Regarding the limitation “wherein the NPNP device comprises an N+ emitter, P+ base, N+ collector region and the P+ contact, the P+ contact being shared with the PMOS transistor”, Cai teaches the dopant-reversed NPNP vertical SCR and the shared P+ contact/source region as explained above for claim 9, but does not expressly label each region of the dopant-reversed NPNP SCR as an N+ emitter, P+ base, and N+ collector region.
However, Campi teaches, in Fig. 1, a vertical NPNP SCR structure including isolated n-well 28, p-well 24, deep n-well 14 and substrate 12. Campi further teaches, in ¶ [0021], teaches emitter region or cathode defined by isolated n-well 28, a gate or base region defined by p-well 24, and a collector region or anode defined by deep n-well 14. Campi further teaches, in ¶ [0018], that isolated n-well 28 is electrically coupled to N+ contact region 30, in ¶ [0017] P-well 24 is electrically coupled to P+ contact region 26, and in ¶ [0016] n-well 14 is electrically coupled to N+ contact region 16, 18 through n-wells 20, 22.
The P+ contact remains shared with the PMOS transistor because Cai teaches, in Fig. 5, that the region corresponding to region 40 is both the final terminal/contact of the vertical SCR and a source/drain region of the triggering MOS transistor 54. In Cai’s dopant reverse PMOS/NPNP embodiment, that shared region is a P+ source region of the PMOS transistor and a P+ contact of the NPNP SCR.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Cai’s dopant-reverse NPNP vertical SCR using Campi’s known NPNP SCR region/contact arrangement, including N+ emitter and collector contacts and P+ base and terminal contacts, in order to provide low-resistance contacts to the SCR emitter, base, collector and final P-type terminal with predictable results as taught by Cai.
Re: Claim 18, Cai discloses all the limitations of claim 17 on which this claim depends.
Regarding the limitation “wherein the NPNP device comprises an N+ emitter, P+ base, N+ collector region and a P+ contact, the P+ contact being shared with the PMOS transistor”, Cia discloses, in Fig. 5 and ¶ [0034], that source/drain regions 40 and 44 act as source/drain regions of triggering MOS transistor 54, and that regions 40 are also final terminal of the SCR structure 90. In the dopant-reversed NPNP/PMOS embodiment taught by Cia, in ¶ [0083], the region corresponding to N+ region 40 in the illustrated PNPN/NMOS embodiment of Fig. 5 is a P+ region. Therefore, the dopant-reversed region 40 comprises a P+ source region of the PMOS transistor 54 and also a P+ contact/final terminal of the NPNP vertical SCR 90. But Cai does not expressly label each region of the dopant-reversed NPNP SCR as an N+ emitter, P+ base, and N+ collector region.
However, Campi teaches, in Fig. 1, a vertical NPNP SCR structure including isolated n-well 28, p-well 24, deep n-well 14 and substrate 12. Campi further teaches, in ¶ [0021], teaches emitter region or cathode defined by isolated n-well 28, a gate or base region defined by p-well 24, and a collector region or anode defined by deep n-well 14. Campi further teaches, in ¶ [0018], that isolated n-well 28 is electrically coupled to N+ contact region 30, in ¶ [0017] P-well 24 is electrically coupled to P+ contact region 26, and in ¶ [0016] n-well 14 is electrically coupled to N+ contact region 16, 18 through n-wells 20, 22.
The P+ contact remains shared with the PMOS transistor because Cai teaches, in Fig. 5, that the region corresponding to region 40 is both the final terminal/contact of the vertical SCR and a source/drain region of the triggering MOS transistor 54. In Cai’s dopant reverse PMOS/NPNP embodiment, that shared region is a P+ source region of the PMOS transistor and a P+ contact of the NPNP SCR.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Cai’s dopant-reverse NPNP vertical SCR using Campi’s known NPNP SCR region/contact arrangement, including N+ emitter and collector contacts and P+ base and terminal contacts, in order to provide low-resistance contacts to the SCR emitter, base, collector and final P-type terminal with predictable results as taught by Cai.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cai (US 20170069616 A1) in view of Kocon (US 20220271158 A1).
Re: Claim 11, Cai discloses all the limitations of claim 7 on which this claim depends.
Regarding “wherein the lateral PMOS transistor comprises a gate structure comprising silicided polysilicon”, Cai teaches the vertical SCR, lateral PMOS transistor as explained above and also teaches polysilicon gate 50, but is silent regarding the gate structure comprising silicided polysilicon.
However, Kocon teaches a gate structure comprising silicided polysilicon (Kocon teaches that gate electrode 126 may include polysilicon and may also include metal silicide extending down to the gate dielectric layer 124 in a gate architecture referred to as a fully silicided (FUSI) gate).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide Cai’s polysilicon gate 50 with silicide, as taught by Kocon, in order to reduce gate/contact resistance and improve electrical connection of the MOS gate structure (Kocon, ¶ [0074]).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cai (US 20170069616 A1) in view of Bobde (US 20170365710 A1).
Re: Claim 13, Cai discloses all the limitations of claim 1 on which this claim depends.
further comprising a body contact of a first dopant type tied to the semiconductor substrate, the body contact being connecting to ground (Cai teaches, in ¶ [0036], P+ taps 66 that allow P-substrate 64 to be biased, such as to ground. Thus, Cai teaches P+ body/substrate contact tied to the semiconductor substrate and connected to the ground).
Regarding the body contact being interdigitated with a drain region of the triggering device, the drain region being of a second dopant type, Cai teaches that N+ regions 44 are drain regions of triggering MOS transistors 54 and that the P+ taps 66 provide substrate/body biasing, but Cai is silent regarding the P+ taps 66 as being interdigitated with the N+ type drain region 44.
However, Bobde teaches the body contact being interdigitated with a drain region of the triggering device (Bobde teaches, in Fig. 1 and ¶ [0030], a P+ body contact region 18 formed in P-body region 19 for providing an ohmic contact to the P-body region of the MOSFET device, and an N+ drain region 26. Bobde further teaches, in Fig. 6 and ¶ [0047], that N+ drain region 26 form long drain fingers and that P+ body contact regions 18 form long body contact fingers. Bobde also teaches, in its Claim 4, that, in each transistor cell, the body contact region finger is formed interleaved between the source region finger and the drain region finger. Thus, Bobde teaches a body contact of a first dopant type interleaved/interdigitated with a drain region of a second dopant type in a MOSFET layout).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s triggering MOS transistor layout such that grounded P+ body/substrate contact 66 is formed as body-contact fingers interdigitated with the N+ drain regions 44 of triggering MOS transistor 54, as taught by Bobde in order to provide ohmic contact to the body region of the MOS triggering device while implementing the MOS device in a known multi-finger transistor-cell layout (Bobde, ¶ [0030]).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cai (US 20170069616 A1) in view of Russ (US 6770918 B2).
Re: Claim 19, Cai discloses all the limitations of claim 14 on which this claim depends.
Cai is silent regarding
further comprising deep trench isolation structures extending into the semiconductor substrate and surrounding a well, the deep trench isolation structures further isolating the vertical silicon controlled rectifier and lateral triggering device.
However, Russ teaches further comprising deep trench isolation structures extending into the semiconductor substrate and surrounding a well (Russ teaches, in Fig. 4, a ring of deep trench isolation structure DTI 219 and 219 is extending into semiconductor substrate 203/208. Russ also teaches in Fig. 4 and column 9, lines 60-65, N-well 406 is diffused into N-epitaxial layer 208 and is laterally isolated by DTI 219. Because DTI 219 is a ring of deep trench isolation that laterally isolates the active region/well region, DTI 219 surrounds the well region), the deep trench isolation structures further isolating the vertical silicon controlled rectifier and lateral triggering device (Russ teaches, Column 10 lines 40-45, SCR is laterally isolated by DTI 219. Russ also discloses, in Fig. 5A and Column 11, lines 47-54, that the trigger device 105 has a similar semiconductor stack and that lateral isolation of the trigger device’s N-epi layer 508 is provided by a ring of DTI 519).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai’s SCR/triggering MOS transistor structure to include a ring of deep trench isolation structures extending into the semiconductor substrate and surrounding the well region containing the active SCR/triggering device structure, such as Cai’s P-well 60 and deep N-well 62 region, as taught by Russ in order to laterally isolate the active ESD protection device region from surrounding semiconductor regions and adjacent devices.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
Kuo (US 20170287894 A1) and Hsu (US 20140159206 A1) disclose Silicon Controlled Rectifier with triggering device and Electrostatic discharge protection structure.
Conclusion
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/BIPANA ADHIKARI DAWADI/ Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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