Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of Invention I and Species A in the reply filed on 4/29/2026 is acknowledged.
35 U.S.C. § 102 Rejections
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 7, 8, 11, 13, 32, 33, 35 and 37 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Low et al. (US Pub, 20060046352), hereinafter referred to as Low.
Regarding claim 7, Low teaches a method of making a semiconductor device, comprising: providing a first semiconductor die (Low, 100, Fig. 1, para. 13); forming a barrier over the first semiconductor die (Low, 140, 142, 150, 152, Fig. 1, para. 16); disposing a second semiconductor die over the first semiconductor die (Low, 260, 270, Fig. 2, para. 19), wherein the barrier extends completely around the second semiconductor die (Low, 140-143 and 150-153, Fig. 4, paras. 16 and 30); and dispensing an underfill (Low, 360, 370, Fig. 3, para. 24) between the first semiconductor die and second semiconductor die.
Regarding claim 8, Low teaches the method of claim 7, further including forming the barrier by: forming a first insulating layer (Low, 105, paras. 13-14) over the first semiconductor die; and forming a trench (Low, 140, 142, 150m 152, Fig. 1, para. 16) in the first insulating layer.
Regarding claim 11, Low teaches the method of claim 7, further including: forming a conductive layer over the first semiconductor die (Low, para. 14, states 105 has interconnects such as conductive metal lines to connect contacts on the top surface of substrate 105 to contacts on the bottom surface of substrate 105); forming a contact pad over the conductive layer (Low, 102, para. 20, says there may be contacts); and mounting the second semiconductor die to the contact pad (Low 260, 270, , Figs. 2, 3, para. 19).
Regarding claim 13, Low teaches the method of claim 7, further including dispensing the underfill (Low, 360, 370, Fig. 3, para. 24) to completely fill a footprint of the second semiconductor die.
Regarding claim 32, Low teaches a method of making a semiconductor device, comprising: providing a first semiconductor die (Low, 100, Fig. 1, para. 13); forming a barrier over the first semiconductor die (Low, 140, 142, 150, 152, Fig. 1, para. 16); disposing a second semiconductor die over the first semiconductor die (Low, 260, 270, Fig. 2, para. 19), wherein the barrier extends completely around the second semiconductor die (Low, 140-143 and 150-153, Fig. 4, paras. 16 and 30),
Regarding claim 33, Low teaches the method of claim 32, further including forming the barrier by: forming a first insulating layer (Low, 105, paras. 13-14) over the first semiconductor die; and forming a trench (Low, 140, 142, 150m 152, Fig. 1, para. 16) in the first insulating layer.
Regarding claim 35, Low teaches the method of claim 32, further including: forming a conductive layer over the first semiconductor die (Low, para. 14, states 105 has interconnects such as conductive metal lines to connect contacts on the top surface of substrate 105 to contacts on the bottom surface of substrate 105); forming a contact pad over the conductive layer (Low, 102, para. 20, says there may be contacts); and mounting the second semiconductor die to the contact pad (Low 260, 270, , Figs. 2, 3, para. 19).
Regarding claim 37, Low teaches the method of claim 32, further including dispensing an underfill (Low, 360, 370, Fig. 3, para. 24) to completely fill a footprint of the second semiconductor die.
35 U.S.C. § 103 Rejections
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Low as applied to claim 7 above, and further in view of Chen et al. (US Pub. 20170194226), hereinafter referred to as Chen.
Regarding claim 12, Low teaches the method of claim 11, but does not teach further including: forming an under-bump metallization over the first semiconductor die outside a boundary of the barrier; and disposing a solder bump on the under-bump metallization.
However Chen teaches an underfill control structure and method wherein a spacer (Chen 111, Fig. 2A/B, para. 34) acts as the barrier to stop the underfill (Chen, 205, Fig. 2A/B, para. 29) from travelling (Chen, 207, Fig. 2A, para. 33) towards external connection underbump metallization (Chen, 110, Fig. 2A/B) which has the external connection (Chen, 201, Fig. 2A/B, para. 35) disposed on it.
Therefore it would have been obvious to one having ordinary skill in the art to place the underbump metallization and solder bump of Chen outside the barrier of Low to prevent physical contact between the underbump metallization and the underfill, thereby preventing contamination or undesired interactions (Chen, para. 34).
Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Low as applied to claim 35 above, and further in view of Chen.
Regarding claim 36, Low teaches the method of claim 35, but does not teach further including: forming an under-bump metallization over the first semiconductor die outside a boundary of the barrier; and disposing a solder bump on the under-bump metallization.
However Chen teaches an underfill control structure and method wherein a spacer (Chen 111, Fig. 2A/B, para. 34) acts as the barrier to stop the underfill (Chen, 205, Fig. 2A/B, para. 29) from travelling (Chen, 207, Fig. 2A, para. 33) towards external connection underbump metallization (Chen, 110, Fig. 2A/B) which has the external connection (Chen, 201, Fig. 2A/B, para. 35) disposed on it.
Therefore it would have been obvious to one having ordinary skill in the art to place the underbump metallization and solder bump of Chen outside the barrier of Low to prevent physical contact between the underbump metallization and the underfill, thereby preventing contamination or undesired interactions (Chen, para. 34).
Allowable Subject Matter
Claims 1-6 and 26-31 allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, Low teaches a method of making a semiconductor device, comprising: providing a first semiconductor die (Low, 100, Fig. 1, para. 13);
forming a first insulating layer over the first semiconductor die (Low, 105 Fig. 1, paras. 13-14); mounting a second semiconductor die over the first semiconductor die (Low, 260, 270, Fig. 2, para. 19), wherein the recess completely surrounds the second semiconductor die in plan view (Low, 140-143, 150-152, Fig. 4, paras. 16, 30); and dispensing an underfill between the first semiconductor die and second semiconductor die (Low, 360, 370, Fig. 3, para. 24).
While Low teaches forming a trench (grooves 140, 142) in a first insulating layer (substrate 105), Low does not teach, nor does the prior art suggest, forming a second insulating layer over the first insulating layer, wherein a recess forms in the second insulating layer over the trench automatically as part of the formation process of the second insulating layer, or wherein a second semiconductor die is mounted over the second insulating layer.
Claims 2-6 are allowed as depending from allowable claim 1.
Regarding claim 26, Low teaches a method of making a semiconductor device, comprising: providing a first semiconductor die (Low, 100, Fig. 1, para. 13);
forming a first insulating layer over the first semiconductor die (Low, 105 Fig. 1, paras. 13-14); mounting a second semiconductor die over the first semiconductor die (Low, 260, 270, Fig. 2, para. 19), wherein the recess completely surrounds the second semiconductor die in plan view (Low, 140-143, 150-152, Fig. 4, paras. 16, 30); and dispensing an underfill between the first semiconductor die and second semiconductor die (Low, 360, 370, Fig. 3, para. 24).
While Low teaches forming a trench (grooves 140, 142) in a first insulating layer (substrate 105), Low does not teach, nor does the prior art suggest, forming a second insulating layer over the first insulating layer, wherein a recess forms in the second insulating layer over the trench automatically as part of the formation process of the second insulating layer, or wherein a second semiconductor die is mounted over the second insulating layer.
Claims 27-31 are allowed as depending from allowable claim 26.
Claims 9, and 34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 9, Low teaches the method of claim 8, but does not teach, nor does the prior art suggest, further including forming the barrier by forming a second insulating layer over the first insulating layer, wherein a recess is formed in the second insulating layer over the trench automatically as part of the process of forming the second insulating layer.
Regarding claim 34, Low teaches the method of claim 33, but does not teach, nor does the prior art suggest, further including forming the barrier by forming a second insulating layer over the first insulating layer, wherein a recess is formed in the second insulating layer over the trench automatically as part of the process of forming the second insulating layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. .
Hsu et al. (US Patent 7768131) teaches a method wherein a recess is used to control the flow of solder during the mounting of on two semiconductor dies.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:00-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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