Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-17 and cancelation of group II claims 17-20 in the reply filed on 04/15/2026 is acknowledged.
Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5, 7-9, 21, 22 are rejected under 35 U.S.C. 103 as being obvious over United States Patent Application Publication by Huang et al. (US 20210358842 A1; Huang) in view of Korean Patent Publication by YU CHEONG SIK (KR 20080072212 A; Provided machine translation; hereinafter Sik)
Regarding claim 1, Huang discloses a method of forming a semiconductor device, the method comprising:
forming a device layer that comprises nanostructures (54A-C, 55) and a gate structure (102) around the nanostructures (Para. 66, and Figs. 20A-C: where the device layer is formed in a manner to have the nanostructures around the gate structure);
forming a first interconnect structure (120) on a front-side (In this case we will say a “front side” is the top side in Figs. 21A-C of the reference) of the device layer (Para. 69, Figs. 21A-C); and
forming a second interconnect structure (136) on a backside of the device layer opposing the front-side of the device layer (Para. 88, Figs. 28A-I, where the second interconnect structure 136 is formed on the opposing side of the device layer compared to the side the first interconnect structure is on), comprising:
forming a dielectric layer (138A-F, [138]) along the backside of the device layer using a first dielectric material (Para. 89, “The fourth dielectric layers 138 may comprise dielectric materials”);
forming a first conductive feature (140A-C) and a second conductive feature (140A-C) in the dielectric layer (Para. 90, where any of 140A-C can be the first conductive feature and any other of 140A-C can be the second conductive feature);
forming a first barrier layer (141) and a second barrier layer (141) along a first sidewall of the first conductive feature facing the second conductive feature and along a second sidewall of the second conductive feature facing the first conductive feature respectively (Para. 89, Fig. 28G, where the multiple high-k dielectric layers 141 are each be a barrier layer and they are placed above and below each of the conductive features); and
forming a second dielectric material (138) different from the first dielectric material (Para. 89, where the multiple layers of dielectric material 138 can comprise a layer of low-k dielectric materials),
However, Huang fails to disclose the step of forming an opening in the dielectric layer by removing portions of the dielectric layer disposed between the first conductive feature and the second conductive feature and forming a second dielectric material in the opening between the first barrier layer and the second barrier layer.
In a similar field of endeavor, Sik discloses a method for forming a semiconductor device including the forming of horizontal layers disposed on the side of a semiconductor device where in those horizontal layers include the forming of an opening (135) by removing portions of the dielectric layer (130) disposed between the first conductive feature (155) and the second conductive feature (An Adjacent 155) (Fig. 1f). And then forming a second dielectric material (180) in the opening between the first barrier layer (145) and the second barrier layer (170) (Figs. 1f-1j).
In view of the disclosure of Sik, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Sik to Huang at the time the instant application was filed to incorporate forming an opening in the dielectric layer by removing portions of the dielectric disposed between first and second conductive feature and forming a second dielectric material in the opening. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages such as reducing the RC delay, which improves the performance of the device (Sik: Provided machine translation End of page 13, beginning of page 14).
Regarding claim 2, the combination of Huang and Sik discloses the method of claim 1, and further Huang discloses wherein a first dielectric constant of the first dielectric material is lower than a second dielectric constant of the second dielectric material (Huang: Para. 89, where the layers 138 may be high-k while a remainder may be low-k dielectric).
Regarding claim 3, the combination of Huang and Sik discloses the method of claim 2, wherein the first dielectric material is a low-K dielectric material, and the second dielectric material is a high-K dielectric material (Huang: Para. 89).
Regarding claim 4, the combination of Huang and Sik discloses the method of claim 1, and further Sik discloses wherein forming the opening is performed before forming the first barrier layer and the second barrier layer (Sik: See Fig. 1f, where the opening if formed but the second barrier layer has yet to be formed, meaning the opening is formed before forming the first and second barrier layers), wherein after removing the portions of the dielectric layer to form the opening, the opening exposes the first sidewall of the first conductive feature and exposes the second sidewall of the second conductive feature (Sik: Fig. 1f, where the sidewalls of the first and second conductive elements (155) are exposed).
Regarding claim 5, the combination of Huang and Sik discloses the method of claim 4, and further Sik discloses wherein forming the first barrier layer and the second barrier layer comprises:
lining sidewalls and a bottom of the opening with a barrier material (Sik: Fig. 1g, second barrier layer (170) lines sidewalls and bottom of the opening, where bottom of the opening can be considered the top of the figure); and
after the lining, removing the barrier material from the bottom of the opening (Sik: Fig. 1i, where a planarization process removes barrier material from the bottom of the opening), wherein a first remaining portion of the barrier material along the first sidewall of the first conductive feature forms the first barrier layer, and a second remaining portion of the barrier material along the second sidewall of the second conductive feature forms the second barrier layer (Sik: Fig. 1g).
Regarding claim 7, the combination of Huang and Sik discloses the method of claim 5, and further Sik discloses wherein forming the second dielectric material (180) comprises, after forming the first barrier layer and the second barrier layer, filling the opening with the second dielectric material (Sik: Fig 1h, where opening 135 is filled with second dielectric material 180), wherein after the filling, the second dielectric material extends continuously from the first barrier layer to the second barrier layer (Sik: Fig. 1i).
Regarding claim 8, the combination of Huang and Sik discloses the method of claim 1, and further Sik discloses wherein forming the opening is performed after forming the first barrier layer and the second barrier layer (Sik: Fig. 1f, where the opening 135 is formed but the second barrier portion 170 has not been formed) , wherein after removing the portions of the dielectric layer to form the opening, the opening exposes the first barrier layer disposed along the first sidewall of the first conductive feature and exposes the second barrier layer disposed along the second sidewall of the second conductive feature (Sik: Fig. 1g).
Regarding claim 9, the combination of Huang and Sik discloses the method of claim 8, and further Sik discloses wherein forming the second dielectric material (Sik: 180) comprises:
lining sidewalls and a bottom of the opening with the second dielectric material (Fig. 1h, where second dielectric material 180 is disposed in and fills the opening 135), wherein a first portion of the second dielectric material extends along the first barrier layer, a second portion of the second dielectric material extends along the second barrier layer, and a third portion of the second dielectric material extends along the bottom of the opening (Sik: Fig. 1h, the second dielectric material 180 extends along the first barrier layer, the second barrier layer, and the bottom of the opening); and
after lining the sidewalls and the bottom of the opening with the second dielectric material, removing the third portion of the second dielectric material from the bottom of the opening (Sik: The bottom of the opening can be considered the upper portion in the figure. After the planarization process as shown in Fig. 1i, the third portion of the second dielectric material from the bottom of the opening is removed).
Regarding claim 21, Huang discloses a method of forming a semiconductor device, the method comprising:
forming a device layer that comprises nanostructures (54A-C, 55) and a gate structure (102) around the nanostructures (Para. 66, and Figs. 20A-C: where the device layer is formed in a manner to have the nanostructures around the gate structure);
forming a first interconnect structure (120) on a first side (In this case we will say a “first side” is the top side in Figs. 21A-C of the reference) of the device layer (Para. 69, Figs. 21A-C); and
forming a second interconnect structure (136) on a second side of the device layer opposing the first side of the device layer (Para. 88, Figs. 28A-I, where the second interconnect structure 136 is formed on the opposing side [second side] of the device layer compared to the side the first interconnect structure is on), comprising:
forming a first dielectric layer (anyone of 138A-F, [138]) along the second side of the device layer,
forming a first conductive feature (140A-C) and a second conductive feature (140A-C) in the second dielectric layer (Para. 90, where any of 140A-C can be the first conductive feature and any other of 140A-C can be the second conductive feature);
forming a metal-insulator-metal (MIM) capacitor (142) in the second dielectric layer between the first conductive feature and the second conductive feature (Fig. 28E), comprising:
forming a first barrier layer (141) and a second barrier layer (141) along a first sidewall of the first conductive feature facing the second conductive feature and along a second sidewall of the second conductive feature facing the first conductive feature respectively (Para. 89, Fig. 28G, where the multiple high-k dielectric layers 141 are each be a barrier layer and they are placed above and below each of the conductive features); and
forming a second dielectric material in the second dielectric layer between the first barrier layer and the second barrier layer, wherein the second dielectric material is different from the first dielectric material.
forming a second dielectric material (138) in the second dielectric layer different from the barrier layer, wherein the second dielectric material is different from the first dielectric material (Para. 89, where the multiple layers of dielectric material 138 can comprise a layer of low-k dielectric materials),
However, Huang fails to disclose the step of forming an etch stop layer (ESL) over the first dielectric layer and the step of forming a second dielectric layer over the ESL, wherein the first dielectric layer and the second dielectric layer are formed of a first dielectric material;
In a similar field of endeavor, Sik discloses a method for forming a semiconductor device including the forming of horizontal layers disposed on the side of a semiconductor device where in those horizontal layers include the forming etch stop layer (130) over the first dielectric layer (110), forming a second dielectric layer (180) over the ESL (Sik: Fig. 1h).
In view of the disclosure of Sik, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Sik to Huang at the time the instant application was filed to incorporate forming an the ESL over the first dielectric layer and the step of forming the second dielectric layer over the ESL layer. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages such as accurately stopping the planarization process at the desired depth (Sik: Provided machine translation End of page 11, beginning of page 12).
Regarding claim 22, the combination of Huang and Sik discloses the method of claim 21, and further Huang discloses wherein the second dielectric material has a higher dielectric constant than the first dielectric material (Huang: Para. 89, where the layers 138 may be high-k while a remainder may be low-k dielectric).
Allowable Subject Matter
Claims 12-17 allowed.
Claims 6, 10-11, 23 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, the combination of Huang and Sik discloses the method of claim 5, However, the combination fails to disclose wherein removing the barrier material comprises performing an anisotropic etching process to remove the barrier material from the bottom of the opening.
Removing the barrier material from the bottom of the opening using an anisotropic method doesn’t make sense for the combination of references cited as the references use a CPM planarization method and even prepare a hard mask 165 as an etch stop in order to perform that process. There is not a reasonable motivation to use an anisotropic etching process which is more tailored to directional etching without the use of hindsight bias from the instant application. Examiner believes that claim 6 is novel for at least these reasons.
Regarding claim 10, the combination of Huang and Sik discloses the method of claim 9, however, the prior art of record fails to disclose “after removing the third portion of the second dielectric material, lining the sidewalls and the bottom of the opening with a barrier material” along with the other limitations in the claim. The prior art fails to further provide additional space in the opening to deposit anything else in the opening after the deposition of the second dielectric material.
Claim 11, is found to contain allowable subject matter because of at least it is dependent on claim 10.
Regarding claim 12, Huang discloses a method of forming a semiconductor device, the method comprising:
forming a device layer that comprises nanostructures (54A-C, 55) and a gate structure (102) around the nanostructures (Para. 66, and Figs. 20A-C: where the device layer is formed in a manner to have the nanostructures around the gate structure);
forming a first interconnect structure (120) on a first side (In this case we will say a “first side” is the top side in Figs. 21A-C of the reference) of the device layer (Para. 69, Figs. 21A-C); and
forming a second interconnect structure (136) on a second side of the device layer opposing the first side of the device layer (Para. 88, Figs. 28A-I, where the second interconnect structure 136 is formed on the opposing side [second side] of the device layer compared to the side the first interconnect structure is on), comprising:
forming a dielectric layer (138A-F, [138]) along the second side of the device layer using a first dielectric material (Para. 89, “The fourth dielectric layers 138 may comprise dielectric materials”);
forming a first conductive feature (140A-C) in the dielectric layer (Para. 90, where any of 140A-C can be the first conductive feature and any other of 140A-C can be the second conductive feature, all of which are surrounded by dielectric layers 138) and surrounded by a first barrier layer (141)
forming a second conductive feature (140A-C) in the dielectric layer (Para. 90, where any of 140A-C can be the first conductive feature and any other of 140A-C can be the second conductive feature, all of which are surrounded by dielectric layers 138) and surrounded by a second barrier layer (141 - different 141);
forming a second dielectric material (138) different from the first dielectric material (Para. 89, where the multiple layers of dielectric material 138 can comprise a layer of low-k dielectric materials),
However, Huang fails to disclose the steps of removing portions of the dielectric layer disposed between the first conductive feature and the second conductive feature to form an opening in the dielectric layer, the opening exposing a first sidewall of the first barrier layer and a second sidewall of the second barrier layer,
forming the second dielectric material along the first sidewall of the first barrier layer and along the second sidewall of the second barrier layer;
after forming the second dielectric material, lining sidewalls and a bottom of the opening with a third barrier layer; and
In a similar field of endeavor, Sik discloses a method for forming a semiconductor device including the forming of horizontal layers disposed on the side of a semiconductor device where in those horizontal layers include the forming of an opening (135) by removing portions of the dielectric layer (130) disposed between the first conductive feature (155) and the second conductive feature (An Adjacent 155) (Fig. 1f). And then forming a second dielectric material (180) in the opening [and along a first and second sidewall] between the first barrier layer (145) and the second barrier layer (170) (Figs. 1f-1j).
In view of the disclosure of Sik, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Sik to Huang at the time the instant application was filed to incorporate forming an opening in the dielectric layer by removing portions of the dielectric disposed between first and second conductive feature and forming a second dielectric material in the opening. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages such as reducing the RC delay, which improves the performance of the device (Sik: Provided machine translation End of page 13, beginning of page 14).
However, the prior art or record above fails to disclose “after forming the third barrier layer, filling the opening with an electrically conductive material.” Along with the other limitations of the claim. The prior art fails to further provide additional space in the opening to deposit anything more in the opening after the deposition of the second dielectric material. There also fails to be any reason or motivation to change or add an additional dielectric material deposited in the opening as the second dielectric material is used to fill the rest of the opening before planarization.
Additionally Claim 13-17, are also allowable based on their dependency to allowed claim 12.
Regarding claim 23, the combination of Huang and Sik discloses the method of claim 22, however, the prior art of record fails to disclose “wherein after forming the second dielectric material, a portion of the ESL extends along a lower surface of the second dielectric material facing the first dielectric layer.” The prior art of record fails to provide that the etch stop layer can have a face that extends along a lower surface of the second dielectric mater and said face, faces the first dielectric layer.
Conclusion
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/DANIEL J HIBBERT/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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