DETAILED ACTION
Election/Restrictions
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/26/2026
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/03/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 discloses “wherein forming the second metal via comprises compressing a portion of the dielectric isolation layer…” which improperly presents a passive physical response of the dielectric isolation layer, which is caused by the weight of the via material, as an affirmative process step that the method performs. In other words, for processes, the claim limitations will define steps or acts to be performed. The claim language is ambiguous as to whether “compressing” is a step actively performed or merely a description of a material response.
Claim 3 is also rejected based on its dependency on claim 2.
Furthermore, claim 2 discloses “wherein forming the second metal via comprises compressing a portion of the dielectric isolation layer directly below material of the second metal via.”
Applicant’s specification discloses the following:
Abstract: … forming a first metal via in the first opening and a second metal via in the second opening
[0041] Metal vias 40A are formed in openings 90A over TSVs 16, and metal vias 40B are formed in openings 90B over metal posts 62.
[0080] … wherein the second metal via is embedded in the second dielectric layer and connected to the metal post, and wherein a height of the first metal via is greater than a height of the second metal via.
Fig. 13 of the specification shows a first opening 90A above TSV’s 16 and a second opening 90B above metal posts 62.
The wording in Claim 2 appears to be inconsistent with the specification and drawings. Claim 2 should state “wherein forming the first metal via comprises compressing a portion of the dielectric isolation layer directly below material of the first metal via” in order to be consistent with the specification. Paragraph [0080] states that the second metal via is above the metal post. Furthermore, the first metal via is above the TSV’s 16 as shown in the figures.
Claim 3 discloses “wherein a height of the second metal via is greater than a height of the first metal via.”
The claim should state “wherein a height of the first metal via is greater than a height of the second metal via” In order to be consistent with Fig. 14 which shows a first metal via 40A having a greater height than second metal via 40B.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over OLSON et al. (US 20230238304 A1), hereinafter “Olson,” in view of YU et al. (US 20180082978 A1), hereinafter “Yu,” and CHENG et al. (US 20230187364 A1), hereinafter “Cheng.”
Re: Independent Claim 1, Olson discloses a method (¶0002: fully molded semiconductor package and method of making) comprising:
forming a first redistribution structure over a substrate (Fig. 2A: interconnect structure 50, i.e., first redistribution structure; See ¶0053; Also see Fig. 3A which shows an alternate embodiment with first RDL 100);
forming a metal post over the first redistribution structure (Fig. 2B: conductive interconnects 72, i.e., metal posts; see ¶0057);
attaching a first device die to the first redistribution structure (Fig. 2B: component 14, i.e., device die; ¶0060: semiconductor die), the first device die comprising a through via embedded in a semiconductor substrate (Fig. 2B shows device die 14 with TSV’s 27 embedded);
encapsulating the metal post and the first device die in an encapsulant (Fig. 2C: mold compound 76 encapsulates device die 14 and metal posts 72; See ¶0062: mold compound or encapsulant 76 deposited over … embedded component 14 and the conductive interconnects 72), a first top surface of the encapsulant being level with a second top surface of the semiconductor substrate (Fig. 2C shows a top surface of encapsulant, first top surface, and top surface of device, i.e., second top surface, being level with each other after grinding process; see ¶0064);
…
forming a first metal via in the first opening and a second metal via in the second opening (Fig. 2E shows via’s for both the device die, first openings, and the metal posts 72, i.e., second openings; ¶0068: conductive vias formed as part of the build-up interconnect structure 100 (and more specifically, e.g., the first conductive layer 104 as described below) may form the second electrical interconnect structure coupled to a second end of the TSVs 27); and
forming a second redistribution structure over the dielectric layer (Fig. 3A shows a second redistribution layer 50 above a first redistribution layer 100; ¶0054: build-up interconnect structure 50 can optionally comprise one or more insulating or passivation layers 52, i.e., dielectric layers), the second redistribution structure being electrically connected to the first metal via and the second metal via (Fig. 3A: second redistribution layer 50 is electrically connected to first metal via’s for the device die 114 and also the second metal via’s for the metal posts; Fig. 6B also shows via connections to both device die and metal posts).
However, Olson does not specifically disclose recessing the second top surface to expose the through via; forming a dielectric isolation layer around the through via; forming a dielectric layer over the dielectric isolation layer; etching the dielectric layer to form a first opening and a second opening in the dielectric layer;
In a similar field of endeavor, Yu discloses recessing the second top surface to expose the through via (See Figs. 10-13; Fig. 11: recesses 144 are formed through top surface of die, i.e., second top surface, to expose metal pillar 140A (see Fig. 4 and ¶0019); Also see ¶0030);
forming a dielectric isolation layer around the through via (Fig. 12: dielectric layer 58 is formed around metal pillar 140A; ¶0030: replacement of die-attach films 134 with dielectric layers 58);
…
forming a dielectric layer over the dielectric isolation layer (¶0031: FIG. 14 illustrates the formation of dielectric layers 60 and RDLs 62);
Reasons for why one of ordinary skill in the art would be motivated to combine the teachings of Olson in view of Yu are provided by Cheng. Cheng discloses a semiconductor chip device that includes an interconnect chip having TSV’s at least partially encased in a molding layer (See Fig. 5: TSV’s 180). After the TSV’s are exposed by grinding, Cheng teaches depositing an electrically insulating layer over the molded structure and the exposed TSV ends (See Fig. 6: insulating layer 65). Cheng expressly states that such insulating layers can include polyimide (¶0066: insulating layer 65 can include polyimide) and that the dielectric layers function as stress buffers and isolation films while enabling redistribution layer routing and the formation of vias to the TSV’s (¶0070 states that polyimide/polybenzoxazoles (PBO) act as stress buffers and isolation films. Also see ¶0072: insulating layer 140, i.e., polyimide/PBO is capable of being laser drilled or etched to form openings to accommodate vias.). These teachings of Cheng provide motivation to modify Olson’s molded TSV die structure by incorporating the polyimide (or equivalent organic dielectric) fill process of Yu above the die.
Furthermore, Yu does not clearly/specifically disclose etching the dielectric layer to form a first opening and a second opening in the dielectric layer.
Cheng further discloses etching the dielectric layer to form a first opening and a second opening in the dielectric layer (Fig. 13: dielectric layer 90 with openings 112 above a die, i.e., first opening, and openings 112 above a conductive structure 130, i.e., second openings);
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the process disclosed in Olson by applying the polyimide/PBO recess and fill process taught by Yu in order to provide electrical isolation around the exposed vias, act as a stress buffer, protect the underlying structure, and enable subsequent formation of openings and metal vias for redistribution routing. Such a modification would have been a predictable use of a known technique to achieve the recognized benefits expressly taught by Cheng (See Cheng, ¶0066, ¶0070 and ¶0072).
Re: Claim 2, the combination of Olson in view of Yu and Cheng discloses the method of claim 1.
Cheng further discloses wherein forming the second metal via comprises compressing a portion of the dielectric isolation layer directly below material of the second metal via (Figs. 14 and 15 show metal via’s 100 embedded in dielectric layer 90 and above a dielectric isolation layer 65, i.e., second metal via’s, above the die as shown in Figs. 6 and 7 which causes a compression effect wherein the via to presses into a portion of the dielectric isolation layer 65).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the combination taught by Olson in view of Yu in order to provide electrical isolation around the exposed vias, act as a stress buffer, protect the underlying structure, and enable subsequent formation of openings and metal vias for redistribution routing. Such a modification would have been a predictable use of a known technique to achieve the recognized benefits expressly taught by Cheng (See Cheng, ¶0066, ¶0070 and ¶0072).
Re: Claim 3, the combination of Olson in view of Yu and Cheng discloses the method of claim 2.
Cheng further discloses wherein a height of the second metal via is greater than a height of the first metal via (Figs. 14 and 15 show metal via’s 100 embedded in dielectric layer 90 and above a dielectric isolation layer 65, i.e., second metal via’s, above the die as shown in Figs. 6 and 7 which causes a compression effect wherein the via to presses into a portion of the dielectric isolation layer 65 and elongates in a downward direction, i.e., has a greater height than a via 100 above the conductive metal pillar 130; Figs. 14 and 15 also show via’s 100 embedded in dielectric layer 90 which are located above conductive pillars 130 which are less prone to compression by the weight of the metal via 110).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the combination taught by Olson in view of Yu in order to provide electrical isolation around the exposed vias, act as a stress buffer, protect the underlying structure, and enable subsequent formation of openings and metal vias for redistribution routing. Such a modification would have been a predictable use of a known technique to achieve the recognized benefits expressly taught by Cheng (See Cheng, ¶0066, ¶0070 and ¶0072).
Re: Claim 4, the combination of Olson in view of Yu and Cheng discloses the method of claim 1.
Olson further discloses wherein the metal post is electrically interposed between the first redistribution structure and the second redistribution structure (Figs. 3A and 3B show metal posts 72 electrically interposed between first and second RDL’s).
Re: Claim 5, the combination of Olson in view of Yu and Cheng discloses the method of claim 1.
Olson further discloses wherein a front side of the first device die is attached to and electrically coupled to the first redistribution structure (Fig. 3A shows wherein a backside surface of device die 114, i.e., front side, is electrically coupled to a first RDL 100; ¶0043: Each of the components 14 comprises a backside or back surface 18 and an active surface 20 opposite the backside 18. Active surface 20 may contain analog or digital circuits).
Re: Claim 6, the combination of Olson in view of Yu and Cheng discloses the method of claim 5.
Olson further discloses wherein the through via is electrically interposed between the first redistribution structure and the second redistribution structure (Fig. 3A shows through via in device die 114 electrically interposed between first (100) and second (50) RDL’s).
Re: Claim 7, the combination of Olson in view of Yu and Cheng discloses the method of claim 1.
Yu further discloses wherein the dielectric isolation layer comprises an organic material (Fig. 13: dielectric material 58, i.e., dielectric isolation layer; ¶0030: dielectric material 58 is disposed, wherein dielectric material 58 fills recesses 144… dielectric material 58 is formed of polybenzoxazole (PBO), polyimide, i.e., an organic material).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the process disclosed in Olson by applying the polyimide/PBO recess and fill process taught by Yu in order to provide electrical isolation around the exposed vias, act as a stress buffer, protect the underlying structure, and enable subsequent formation of openings and metal vias for redistribution routing. Such a modification would have been a predictable use of a known technique to achieve the recognized benefits expressly taught by Cheng.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over OLSON et al. (US 20230238304 A1) in view of YU et al. (US 201800082978 A1), CHENG et al. (US 20230187364 A1) and HINER et al. (US 20230154893 A1), hereinafter “Hiner.”
Re: Claim 8, the combination of Olson in view of Yu and Cheng discloses the method of claim 1.
Olson also discloses further comprising forming the device die (See Fig. 1B: device die 14), wherein forming the device die comprises:
forming the through via partially through the semiconductor substrate (Fig. 1B: embedded device 14 comprising TSVs 27);
forming an interconnect structure over the through via (Fig. 1C and 1D show conductive interconnect 28);
…
thinning at least a portion of the semiconductor substrate (See Fig. 1B; ¶0043: TSVs 27 will extend from the active surface to the backside of the component 14 when complete, which will include removing any excess wafer material remaining from the TSVs during manufacture to expose the backside for electrical connection.);
…
While Olson discloses device dies with an interconnect structure and also thinning in Fig. 1B, the combination of Olson in view of Yu and Cheng do not show attaching the interconnect structure to a first carrier; attaching a second carrier to the semiconductor substrate; and removing the first carrier.
In a similar field of endeavor, Hiner discloses
attaching the interconnect structure to a first carrier (See Fig. 1, steps 115-145; Fig. 2E shows device dies on a first carrier 221 followed by a step of thinning in Fig. 2F);
attaching a second carrier to the semiconductor substrate (Fig. 2G shows a second carrier 231); and
removing the first carrier (Fig. 2H shows wherein a first carrier 221 has been removed).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to included device die carriers in order to facilitate and/or increase the manufacturability of the semiconductor device or package (See Hiner, ¶0029).
Re: Claim 9, the combination of Olson in view of Yu, Cheng, and Hiner discloses the method of claim 8.
Yu also discloses further comprising:
attaching a second device die and a third device die to the second redistribution structure (Fig. 16 illustrates the bonding of package components 66; See ¶0032);
removing the substrate (Figs. 17 and 18 show before and after removal of carrier 54); and
forming an electrical connector along the first redistribution structure (Fig. 18 shows solder regions 70 may be formed on UBMs 50).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have applied the process disclosed in Yu in order to place package components to be directly over their voltage suppliers in order to minimize the length of metal lines which directly minimizes voltage drop caused by resistance (See Yu, ¶0033).
Claims 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over OLSON et al. (US 20230238304 A1) in view of HINER et al. (US 20230154893 A1), YU et al. (US 20180082978 A1), and CHENG et al. (US 20230187364 A1).
Re: Independent Claim 10, Olson discloses a method (¶0002: fully molded semiconductor package and method of making) comprising:
forming a device die (See Figs. 1B-1D: device die 14), forming the device die comprising:
forming an interconnect structure over a front side of a semiconductor substrate (Fig. 1C and 1D show conductive interconnect 28), a through via extending partially through the semiconductor substrate (Fig. 1B: embedded device 14 comprising TSVs 27);
forming electrical connectors over the interconnect structure (Figs. 1B and 1C show bumps 30, i.e., electrical connectors);
…
thinning a back side of the semiconductor substrate (See Fig. 1B; ¶0043: TSVs 27 will extend from the active surface to the backside of the component 14 when complete, which will include removing any excess wafer material remaining from the TSVs during manufacture to expose the backside for electrical connection.);
…
…
singulating the semiconductor substrate (Fig. 1C shows singulation);
forming a first redistribution structure over a first carrier substrate (Fig. 2B: RDL 50);
forming a metal post over the first redistribution structure (Fig. 2B: metal posts 72);
attaching the electrical connectors of the device die to the first redistribution structure (Figs. 2B and 2C show die 30 being attached to RDL 50);
encapsulating the metal post and the device die in an encapsulant (Fig. 2C: mold compound 76);
recessing the back side of the semiconductor substrate below a top end of the through via (Fig. 2C shows a top surface of encapsulant, first top surface, and top surface of device, i.e., second top surface, being level with each other after grinding process; see ¶0064);
…
While Olson discloses device dies with an interconnect structure and also thinning in Fig. 1B, Olson does not clearly/specifically disclose attaching a first carrier to the electrical connectors using a glue; attaching a second carrier to the back side of the semiconductor substrate; removing the first carrier; and depositing a dielectric isolation layer around the top end of the through via; forming a buffer structure over the dielectric isolation layer, the buffer structure comprising a first metal via and a second metal via embedded in a dielectric layer.
In a similar field of endeavor, Hiner discloses attaching a first carrier to the electrical connectors using a glue (See Fig. 1, steps 115-145; Fig. 2C: adhesive 223, i.e., glue; Fig. 2E shows device dies on a first carrier 221 followed by a step of thinning in Fig. 2F);
attaching a second carrier to the back side of the semiconductor substrate (Fig. 2G shows a second carrier 231);
removing the first carrier (Fig. 2H shows wherein a first carrier 221 has been removed).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to included device die carriers in order to facilitate and/or increase the manufacturability of the semiconductor device or package (See Hiner, ¶0029).
However, the combination of Olson in view of Yu does not specifically disclose depositing a dielectric isolation layer around the top end of the through via; forming a buffer structure over the dielectric isolation layer, the buffer structure comprising a first metal via and a second metal via embedded in a dielectric layer.
In a similar field of endeavor, Yu discloses depositing a dielectric isolation layer around the top end of the through via (See Figs. 10-13; Fig. 11: recesses 144 are formed through top surface of die, i.e., second top surface, to expose metal pillar 140A (see Fig. 4 and ¶0019); Fig. 12: dielectric layer 58 is formed around metal pillar 140A; ¶0030: replacement of die-attach films 134 with dielectric layers 58); …
Reasons for why one of ordinary skill in the art would be motivated to combine the teachings of Olson in view of Yu is provided by Cheng. Cheng discloses a semiconductor chip device that includes an interconnect chip having TSV’s at least partially encased in a molding layer (See Fig. 5: TSV’s 180). After the TSV’s are exposed by grinding, Cheng teaches depositing an electrically insulating layer over the molded structure and the exposed TSV ends (See Fig. 6: insulating layer 65). Cheng expressly states that such insulating layers can include polyimide (¶0066: insulating layer 65 can include polyimide) and that the dielectric layers function as stress buffers and isolation films while enabling redistribution layer routing and the formation of vias to the TSV’s (¶0070 states that polyimide/polybenzoxazoles (PBO) act as stress buffers and isolation films. Also see ¶0072: insulating layer 140, i.e., polyimide/PBO is capable of being laser drilled or etched to form openings to accommodate vias.). These teachings of Cheng provide motivation to modify Olson’s molded TSV die structure by incorporating the polyimide (or equivalent organic dielectric) fill process of Yu above the die.
Furthermore, Yu does not clearly show forming a buffer structure over the dielectric isolation layer, the buffer structure comprising a first metal via and a second metal via embedded in a dielectric layer.
Cheng further discloses forming a buffer structure over the dielectric isolation layer, the buffer structure comprising a first metal via and a second metal via embedded in a dielectric layer (Fig. 14: dielectric layer 90 with via’s 110 above a die, i.e., first metal via’s, and via’s 110 above a conductive structure 130, i.e., second metal via’s; ¶0070: dielectric layers 90 and 95 are preferably composed of polybenzoxazoles… benzocyclobutene, polyimide).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the process disclosed in Olson by applying the polyimide/PBO recess and fill process taught by Yu in order to provide electrical isolation around the exposed vias, act as a stress buffer, protect the underlying structure, and enable subsequent formation of openings and metal vias for redistribution routing. Such a modification would have been a predictable use of a known technique to achieve the recognized benefits expressly taught by Cheng (See Cheng, ¶0066, ¶0070 and ¶0072).
Re: Claim 11, the combination of Olson in view of Hiner, Yu and Cheng discloses the method of claim 10.
Cheng further discloses wherein the first metal via and the second metal via are coplanar with an upper surface of the dielectric layer (Fig. 14: dielectric layer 90 has first and second metal via’s 110 which are coplanar with an upper surface of layer 90), and
wherein the first metal via extends beyond a lower surface of the dielectric layer and into the dielectric isolation layer (Fig. 14 shows first metal via’s 110, which are above the dielectric isolation layer 65 and the TSV’s embedded in the die, and are compressed towards the polyimide layer which causes the depth of the first metal via to be below the upper surface of the dielectric layer 90.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the combination taught by Olson in view of Heiner and Yu in order to provide electrical isolation around the exposed vias, act as a stress buffer, protect the underlying structure, and enable subsequent formation of openings and metal vias for redistribution routing. Such a modification would have been a predictable use of a known technique to achieve the recognized benefits expressly taught by Cheng (See Cheng, ¶0066, ¶0070 and ¶0072).
Re: Claim 12, the combination of Olson in view of Hiner, Yu and Cheng discloses the method of claim 11.
Cheng further discloses wherein the second metal via is coplanar with the lower surface of the dielectric layer (Fig. 14 shows second metal via 110 above conductive pillars 130 which are coplanar with the lower surface of the dielectric layer due to the fact that they are located above a metal which does not compress as easily as the via’s above the polyimide layer above the die).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the combination taught by Olson in view of Heiner and Yu in order to provide electrical isolation around the exposed vias, act as a stress buffer, protect the underlying structure, and enable subsequent formation of openings and metal vias for redistribution routing. Such a modification would have been a predictable use of a known technique to achieve the recognized benefits expressly taught by Cheng (See Cheng, ¶0066, ¶0070 and ¶0072).
Re: Claim 13, the combination of Olson in view of Hiner, Yu and Cheng discloses the method of claim 10.
Yu further discloses … a top surface of the through via being coplanar with a top surface of the portion of the dielectric isolation layer (Fig. 13 shows a top surface of the through via being coplanar with a top portion of polyimide layer 58), …
Reasons for why one of ordinary skill in the art would be motivated to combine the teachings of Olson in view of Yu is provided by Cheng. Cheng discloses a semiconductor chip device that includes an interconnect chip having TSV’s at least partially encased in a molding layer (See Fig. 5: TSV’s 180). After the TSV’s are exposed by grinding, Cheng teaches depositing an electrically insulating layer over the molded structure and the exposed TSV ends (See Fig. 6: insulating layer 65). Cheng expressly states that such insulating layers can include polyimide (¶0066: insulating layer 65 can include polyimide) and that the dielectric layers function as stress buffers and isolation films while enabling redistribution layer routing and the formation of vias to the TSV’s (¶0070 states that polyimide/polybenzoxazoles (PBO) act as stress buffers and isolation films. Also see ¶0072: insulating layer 140, i.e., polyimide/PBO is capable of being laser drilled or etched to form openings to accommodate vias.). These teachings of Cheng provide motivation to modify Olson’s molded TSV die structure by incorporating the polyimide (or equivalent organic dielectric) fill process of Yu above the die.
However, Yu does not clearly/specifically disclose wherein forming the buffer structure comprises:
depositing the dielectric layer over the encapsulant and the dielectric isolation layer;
forming a first opening and a second opening in the dielectric layer, the first opening exposing the through via and a portion of the dielectric isolation layer, …,
…the second opening exposing the metal post; and
depositing a conductive material in the first opening and the second opening.
Cheng further discloses wherein forming the buffer structure comprises:
depositing the dielectric layer over the encapsulant and the dielectric isolation layer (Fig. 13: dielectric layer 90 is above encapsulant and dielectric isolation layer, i.e., polyimide layer);
forming a first opening and a second opening in the dielectric layer (Fig. 13: openings 112 above die and conductive pillars), the first opening exposing the through via and a portion of the dielectric isolation layer (Fig. 13: shows opening above via’s embedded in die and dielectric isolation layer, i.e., polyimide layer),
…the second opening exposing the metal post (Fig. 13: via opening 112 above conductive pillar 130); and
depositing a conductive material in the first opening and the second opening (Fig. 14: conductive material 110 deposited above conductive pillar 130).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the combination taught by Olson in view of Heiner and Yu in order to provide electrical isolation around the exposed vias, act as a stress buffer, protect the underlying structure, and enable subsequent formation of openings and metal vias for redistribution routing. Such a modification would have been a predictable use of a known technique to achieve the recognized benefits expressly taught by Cheng (See Cheng, ¶0066, ¶0070 and ¶0072).
Re: Claim 14, the combination of Olson in view of Hiner, Yu and Cheng discloses the method of claim 13.
Cheng further discloses wherein depositing the conductive material in the first opening comprises compressing the top surface of the portion of the dielectric isolation layer to be below the top surface of the through via (Fig. 14 shows conductive material 110 deposited in the via located above the die and wherein the metal said metal via is also above the polyimide layer which caused a compressive force/weight on the top surface of the polyimide layer.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the combination taught by Olson in view of Heiner and Yu in order to provide electrical isolation around the exposed vias, act as a stress buffer, protect the underlying structure, and enable subsequent formation of openings and metal vias for redistribution routing. Such a modification would have been a predictable use of a known technique to achieve the recognized benefits expressly taught by Cheng (See Cheng, ¶0066, ¶0070 and ¶0072).
Re: Claim 15, the combination of Olson in view of Hiner, Yu and Cheng discloses the method of claim 10.
Olson also discloses further comprising:
forming a second redistribution structure over the buffer structure (Fig. 3A shows a second redistribution layer 50 above a first redistribution layer 100; ¶0054: build-up interconnect structure 50 can optionally comprise one or more insulating or passivation layers 52, i.e., dielectric layers);
attaching a memory die and a logic die over the second redistribution structure (¶0076: The SoC 122 may comprise a large semiconductor die 124, such as memory device, microprocessor; ¶0093: one or more semiconductor die 124 over the frontside build-up interconnect structure 50); and
forming external connectors along the first redistribution structure (Fig. 2G shows external connectors 114 and 116 along first RDL 100).
Allowable Subject Matter
Claims 21-25 are allowed.
Claim 21 is includes a method of forming a buffer structure over a dielectric isolation layer for a device die before it is to be placed on a redistribution structure for further processing. Furthermore, claim 21 requires patterning an opening in the dielectric layer to expose the top end of the through substrate via and a portion of the dielectric isolation layer surrounding the top of the through substrate via prior to singulation of the device die and also prior to being placed on a redistribution structure for further processing.
Hines comes closest to the process claimed but does not disclose the additional features of forming a buffer structure over the dielectric isolation layer. Cheng provides a dielectric isolation layer for a device die but does not disclose depositing a dielectric layer over the isolation layer prior to the device die being placed on a redistribution structure.
The prior art of record, alone or in combination, do not teach or make obvious the claim limitations recited in independent claim 21 including:
forming a buffer structure over the dielectric isolation layer, forming the buffer structure comprising:
depositing a dielectric layer over the dielectric isolation layer;
patterning an opening in the dielectric layer to expose the top end of the through substrate via and a portion of the dielectric isolation layer surrounding the top end of the through substrate via; and
depositing a conductive material in the opening to form a metal via in physical contact with the top end of the through substrate via;
forming a metal bump over and electrically coupled to the metal via;
singulating the device wafer to form a device die after forming the buffer structure;
bonding the device die to a first redistribution structure with the interconnect structure facing the first redistribution structure;
encapsulating the device die in an encapsulant, the encapsulant being level with the metal bump after planarization; and
forming a second redistribution structure over the encapsulant and electrically coupled to the metal bump.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
WU et al. (US 20160056087 A1) – Fig. 12A shows a connecting member 414 which is relevant to the how a metal via compresses into a polyimide material 502 when compressed from above which is relevant to the current claims.
CHEN et al. (US 20220223564 A1) – Figs. 25 and 26 show structures which are relevant to the processing of a device die prior to said die being placed on a redistribution structure in the current claims.
SHIH (US 20180102311 A1) – Figs. 1-14 show a process which is very relevant to the current claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEONARD CHANG can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ADROVEL/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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