DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 04/14/2026
Applicant’s election without traverse of Invention I, Device Embodiment 5, Device Modification A1 and B1 in the reply filed on 04/14/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Farooq et al. (US 2016/0293487 A1, hereinafter Farooq ‘487) in view of Xi et al. (US 2002/0060363 A1, hereinafter Xi ‘363), in view of the following arguments.
With respect to Claim 1 Farooq ‘487 discloses a semiconductor device (Fig 1-17), comprising:
a substrate (10, Fig 1, Para [0027]), having a front-side (12, Fig 1, Para [0027]) and a back-side (14, Fig 1, Para [0027]);
an interconnect (32, Fig 1, Para [0029]), disposed over (disclosed in Fig 1 and Para [0029]) the front-side (12) of the substrate (10); and
a vertical connection structure (28/43/44, Fig 11, Para [0039 and 0046]), embedded in (28/44 embedded in 32 disclosed in Fig 11) the interconnect (32) and penetrating through (28/44 penetrating through 10 disclosed in Fig 11) the substrate (10), and comprising:
a first portion (28, Fig 11, Para [0046]), embedded inside (28 embedded inside 32 disclosed in Fig 11) the interconnect (32) and further extending into (28 extending into substrate 10 disclosed in Fig 11) the substrate (10); and
a second portion (43/44, Fig 11, Para [0046]), disposed in the substrate (10) and extending from (43/44 extending from 14 to 28 disclosed in Fig 11) the back-side (14) to the first portion (28), the second portion (43/44) being in contact with (43/44 in contact with 28 disclosed in Fig 11) the first portion (28),
But Farooq ‘487 fails to explicitly discloses wherein an aspect ratio of the second portion is less than an aspect ratio of the first portion.
Nevertheless, in a related endeavor (Fig 1-8 of Xi ‘363), Xi ‘363 teaches wherein an aspect ratio of the second portion (202, Fig 8 of Xi ‘363, Para [0021]) is less than an aspect ratio of the first portion (210, Fig 8 of Xi ‘363, Para [0021]) (Para [0021] discloses aspect ratio of 202 as 1:1 and an aspect ratio of 210 as 4:1).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Xi ‘363’s teaching of an aspect ratio of the second portion is less than an aspect ratio of the first portion into Farooq ‘487’s device. Farooq ‘487 discloses a semiconductor device with a connection structure with a wider and shorter portion on top and a longer and narrower portion on the bottom but Farooq ‘487 does not disclose explicit dimensions or aspect ratios. Xi ‘363 teaches a semiconductor device with a connection structure with a wider and shorter upper portion and a longer and narrower lower portion and teaches that the upper portion has an aspect ratio that is less than the aspect ratio of the lower portion. The ordinary artisan would have been motivated to modify Farooq ‘487 in the manner set forth above, at least, because, as Xi ‘363 teaches in Para [0006] having an connection with a upper portion having a smaller aspect ratio than the lower portion of the connection structure provides less resistance in the structure. Further one of ordinary skill in the art would be motivated to have an upper bonding area with a larger diameter to aid in bonding additional contacts to the device.
As incorporated, the teaching of Xi ‘363 of an aspect ratio of the second portion is less than an aspect ratio of the first portion would be used as the relative aspect ratios of first portion (28) and second portion (43/44) of Farooq ‘487.
With respect to Claim 2 Farooq ‘487 as modified by Xi ‘363 discloses all limitations of the semiconductor device of claim 1, and Farooq ‘487 discloses further wherein the first portion (28) is covered by the back-side (14) of the substrate (10), and the second portion (43/44) is covered by the front-side (12) of the substrate (10)(Fig 11 discloses 28 is covered by the back side 14 of the substrate 10 and that 43/44 is covered by front side 12 of substrate 10).
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With respect to Claim 3 Farooq ‘487 as modified by Xi ‘363 discloses all limitations of the semiconductor device of claim 1, and Farooq ‘487 discloses further wherein along a direction perpendicular (horizontal direction as shown in annotated Fig 11 of Farooq ‘487) to a stacking direction (vertical direction as shown in Fig 11 annotated Fig 11 of Farooq ‘487) of the first portion (28) and the second portion (43/44), a first size (first size of 28 shown in annotated Fig 11 of Farooq ‘487) of the first portion (28) is less than a second size (second size of 28 shown in annotated Fig 11 of Farooq ‘487) of the second portion (43/44)(Annotated Fig 11 of Farooq ‘487 discloses a first size of 28 is less than a second size of 43/44).
Claims 1, 4, 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2014/0118059 A1, hereinafter Kim ‘059) in view of Xi ‘363, in view of the following arguments.
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With respect to Claim 1 Kim ‘059 discloses a semiconductor device, comprising:
a substrate (101 and lower layer 103a, as shown in annotated Fig 1 of Kim ‘059, Para [0027 and 0031]), having a front-side (top of 101 as shown in Fig 1) and a back-side (bottom of 101 and lower layer 103a as shown in Fig 1);
an interconnect (103/104, Fig 1, Para [0036]), disposed over the front-side (top of 101 and lower layer 103a as shown in Fig 1) of the substrate (101 and lower layer 103a); and
a vertical connection structure (105, Fig 1, Para [0035]), embedded in (105 embedded in 103/104 disclosed in Fig 1) the interconnect (103/104) and penetrating through the substrate (101 and lower layer 103a), and comprising:
a first portion (first portion of 105 as shown in annotated Fig 1 of Kim ‘059, hereinafter FP), embedded inside (FP embedded in 103/104 disclosed in annotated Fig 1 of Kim ‘059) the interconnect (103/104) and further extending into (FP extending into 101 and lower layer 103a disclosed in annotated Fig 1 of Kim ‘059) the substrate (101 and lower layer 103a); and
a second portion (second portion of 105 as shown in annotated Fig 1 of Kim ‘059, hereinafter SP), disposed in (SP disposed in 101 and lower layer 103a disclosed in annotated Fig 1 of Kim ‘059) the substrate (101 and lower layer 103a) and extending from (SP extending from back side of 101 and lower layer 103a to FP shown in annotated Fig 1 of Kim ‘059) the back-side (bottom of 101 and lower layer 103a as shown in Fig 1) to the first portion (FP), the second portion (SP) being in contact with the first portion (FP)(SP in contact with FP shown in annotated Fig 1 of Kim ‘059),
But Kim ‘059 fails to explicitly disclose wherein an aspect ratio of the second portion is less than an aspect ratio of the first portion.
Nevertheless, in a related endeavor (Fig 1-8 of Xi ‘363), Xi ‘363 teaches wherein an aspect ratio of the second portion (202, Fig 8 of Xi ‘363, Para [0021]) is less than an aspect ratio of the first portion (210, Fig 8 of Xi ‘363, Para [0021]) (Para [0021] discloses aspect ratio of 202 as 1:1 and an aspect ratio of 210 as 4:1).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Xi ‘363’s teaching of an aspect ratio of the second portion is less than an aspect ratio of the first portion into Kim ‘059’s device. Kim ‘059 discloses a semiconductor device with a connection structure with via extending through a substrate but Kim ‘059 does not disclose explicit dimensions or aspect ratios. Xi ‘363 teaches a semiconductor device with a connection structure with a wider and shorter upper portion and a longer and narrower lower portion and teaches that the upper portion has an aspect ratio that is less than the aspect ratio of the lower portion. The ordinary artisan would have been motivated to modify Kim ‘059 in the manner set forth above, at least, because, as Xi ‘363 teaches in Para [0006] having an connection with a upper portion having a smaller aspect ratio than the lower portion of the connection structure provides less resistance in the structure. Further one of ordinary skill in the art would be motivated to have an upper bonding area with a larger diameter to aid in bonding additional contacts to the device.
As incorporated, the teaching of Xi ‘363 of an aspect ratio of the second portion is less than an aspect ratio of the first portion would be used as the relative aspect ratios of first portion (FP) and second portion (SP) of Kim ‘059.
With respect to Claim 4 Kim ‘059 as modified by Xi ‘363 discloses all limitations of the semiconductor device of claim 1, and Kim ‘059 discloses further comprising:
a ring wall (106, Fig 1, Para [0032]), disposed inside (Fig 1 discloses 106 disposed inside interconnect 103/104) the interconnect (103/104) and laterally surrounding (106 laterally surrounding FP disclosed in Fig 3, Fig 3 discloses 106 laterally surrounding 105 of which FP is a part of, therefore 106 laterally surrounds FP) the first portion (FP),
wherein the second portion (SP) is vertically distant (annotated Fig 1 of Kim ‘059 discloses SP is vertically distant from 106) from the ring wall (106).
With respect to Claim 6 Kim ‘059 as modified by Xi ‘363 discloses all limitations of the semiconductor device of claim 4, and Kim ‘059 wherein in a vertical projection (Fig 1 as shown in annotated Fig 1 of Kim ‘059) along a stacking direction (stacking direction shown in annotated Fig 1 of Kim ‘059) of the first portion (FP) and the second portion (SP), the ring wall (106) has an annulus shape (annular shape of 106 disclosed in Fig 3 and Para [0042]) continuously enclosing the first portion (FP)(Fig 3 discloses 106 continuously encloses 112 which FP is a part of).
With respect to Claim 13 Kim ‘059 as modified by Xi ‘363 discloses all limitations of the semiconductor device of claim 1, and Kim ‘059 further discloses wherein the first portion (FP) comprises a plurality of first portions (plurality of first portions of FP shown in annotated Fig 1_2 of Kim ‘059) arranged next to each, laterally, (annotated Fig 1_2 of Kim ‘059 discloses a plurality of first portions of FP arranged next to each other laterally)
wherein the plurality of first portions (plurality of first portions of FP shown in annotated Fig 1_2 of Kim ‘059) are electrically coupled to each other through the second portion (SP)(annotated Fig 1_2 of Kim ‘059 discloses plurality of first portions of FP are connected to second portion SP, as they are all portions of 105 plurality of first portions of FP are electrically connected through FP).
Claims 5 and 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘059 in view of Xi ‘363 in further view of Itaya et al. (US 2011/0084385 A1, hereinafter Itaya ‘385), in view of the following arguments.
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With respect to Claim 5 Kim ‘059 as modified by Xi ‘363 discloses all limitations of the semiconductor device of claim 4, but Kim ‘059 as modified by Xi ‘363 fails to explicitly disclose wherein in a vertical projection along a stacking direction of the first portion and the second portion, the first portion is confined by an innermost sidewall of the ring walls, and the second portion is confined by an outermost sidewall of the ring wall.
Nevertheless, in a related endeavor (Fig 1-22 of Itaya ‘385), Itaya ‘385 teaches wherein in a vertical projection (vertical projection shown in annotated Fig 3 of Itaya ‘385) along a stacking direction (stacking direction of the TSV1 and P0 shown in annotated Fig 3 of Itaya ‘385) of the first portion (TSV1 as shown in annotated Fig 3 of Itaya ‘385, Para [0052]) and the second portion (P0 as shown in annotated Fig 3 of Itaya ‘385, Para [0052]), the first portion (TSV1) is confined by an innermost sidewall (TSV1 confined by innermost sidewall of 82 shown in annotated Fig 3 of Itaya ‘385) of the ring walls (82, Fig 3 of Itaya ‘385, Para [0056]), and the second portion (P0) is confined by an outermost sidewall (P0 confined by outermost sidewall of 82 shown in annotated Fig 3 of Itaya ‘385) of the ring wall (82).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Itaya ‘385’s wherein in a vertical projection along a stacking direction of the first portion and the second portion, the first portion is confined by an innermost sidewall of the ring walls, and the second portion is confined by an outermost sidewall of the ring wall into Kim ‘059 as modified by Xi ‘363’s device. The ordinary artisan would have been motivated to modify Kim ‘059 as modified by Xi ‘363 in the manner set forth above, at least, because providing the insulating ring outside the TSV (first portion) and the pad (second portion) the ring can provide protection against parasitic capacitance between the pad/TSV and adjacent devices as disclosed by Itaya ‘385 in Para [0010-0016 and 0056].
As incorporated, the teaching of Itaya ‘385 positioning of the ring wall (82) with an innermost wall (innermost wall of 82) confining the first portion (TSV1) and an outermost wall (outermost wall of 82) confining the second portion (P0) would be used in the arrangement of the first portion (FP), the second portion (SP) and the ring wall (106) of Kim ‘059 as modified by Xi ‘363.
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With respect to Claim 7 Kim ‘059 as modified by Xi ‘363 discloses all limitations of the semiconductor device of claim 1, but Kim ‘059 as modified by Xi ‘363 fails to explicitly disclose further comprising:
an additional vertical connection structure, embedded in the interconnect and penetrating through the substrate, the additional vertical connection structure being laterally next to the vertical connection structure, and comprising:
a plurality of third portions, embedded inside the interconnect and further extending into the substrate; and
a fourth portion, disposed in the substrate and extending from the back- side to the plurality of third portions, the fourth portion being in contact with the plurality of third portions,
wherein an aspect ratio of each of the plurality of third portions is greater than an aspect ratio of the fourth portion.
Nevertheless, in a related endeavor (Fig 1-22 of Itaya ‘385), Itaya ‘385 teaches an additional vertical connection structure (TSV1b, Fig 4 of Itaya ‘385, Para [0056]), embedded in the interconnect (81, Fig 4 of Itaya ‘385, Para [0031]) and penetrating through (Fig 4 of Itaya ‘385 discloses TSV1b embedded in 81 and penetrating 80) the substrate (80, Fig 4 of Itaya ‘385, Para [0052]), the additional vertical connection structure (TSV1b) being laterally next to (shown in Fig 4 of Itaya ‘385) the vertical connection structure (TSV1a, Fig 4 of Itaya ‘385, Para [0056]), and comprising: a plurality of third portions (plurality of third portions of TSV1b disclosed in annotated Fig 4 of Itaya ‘385), embedded inside the interconnect (81) and further extending into the substrate (80) (annotated Fig 4 of Itaya ‘385 discloses plurality of third portions of TSV1b embedded in 81 and extending into 80); and a fourth portion (fourth portion shown in annotated Fig 4 of Itaya ‘385, hereinafter 4P), disposed in the substrate (80) and extending from the back-side (bottom of 80 as shown in annotated Fig 4 of Itaya ‘385) to the plurality of third portions (plurality of third portions of TSV1b disclosed in annotated Fig 4 of Itaya ‘385)(annotated Fig 4 of Itaya ‘385 discloses 4P disposed in 80 and extending from bottom of 80), the fourth portion (4P) being in contact with (4P in contact with plurality of third portions of TSV1b shown in annotated Fig 4 of Itaya ‘385) the plurality of third portions (plurality of third portions of TSV1b disclosed in annotated Fig 4 of Itaya ‘385), wherein an aspect ratio (height:width) of each of the plurality of third portions (plurality of third portions of TSV1b disclosed in annotated Fig 4 of Itaya ‘385) is greater than an aspect ratio (height:width) of the fourth portion (4P)(annotated Fig 4 of Itaya ‘385 discloses height:width of plurality of third portions of TSV1b is greater than height:width of 4P).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Itaya ‘385’s teaching of an additional vertical connection structure, embedded in the interconnect and penetrating through the substrate, the additional vertical connection structure being laterally next to the vertical connection structure, and comprising: a plurality of third portions, embedded inside the interconnect and further extending into the substrate; and a fourth portion, disposed in the substrate and extending from the back- side to the plurality of third portions, the fourth portion being in contact with the plurality of third portions, wherein an aspect ratio of each of the plurality of third portions is greater than an aspect ratio of the fourth portion into Kim ‘059 as modified by Xi ‘363’s device. Itaya ‘385 teaches a semiconductor device with TSV through a substrate, interconnects and device layer like Kim ‘059 as modified by Xi ‘363 but Itaya ‘385 teaches that multiples of these structures can be formed in a device. As the multiple of the devices are the same as the original devices, the person of ordinary skill in the art would have a reasonable expectation of success. Further, the ordinary artisan would have been motivated to modify Kim ‘059 as modified by Xi ‘363 in the manner set forth above, at least, because the additional structures added to the device, as taught by Itaya ‘385 would add functionality to the device and making multiple structures in the same device could lead to manufacturing efficiencies.
As incorporated, the additional vertical interconnect structures with the arrangements taught by Itaya ‘385 above would be incorporated into the device of Kim ‘059 as modified by Xi ‘363.
With respect to Claim 8 Kim ‘059 as modified by Xi ‘363 and further modified by Itaya ‘385 discloses all limitations of the semiconductor device of claim 7, and Kim ‘059 as modified by Xi ‘363 and further modified by Itaya ‘385 further discloses wherein the plurality of third portions (plurality of third portions of TSV1b disclosed in annotated Fig 4 of Itaya ‘385 as incorporated above) are covered by the back-side of the substrate (bottom of 80), and the fourth portion (4P) is covered by the front-side of the substrate (top of 80 as shown in annotated Fig 4 of Itaya ‘385)(annotated Fig 4 of Itaya ‘385 discloses plurality of third portions are covered by bottom of 80 and 4P is covered by front side of 80).
With respect to Claim 9 Kim ‘059 as modified by Xi ‘363 and further modified by Itaya ‘385 discloses all limitations of the semiconductor device of claim 7, and Kim ‘059 as modified by Xi ‘363 and further modified by Itaya ‘385 discloses further wherein along a direction perpendicular (horizontal direction) to a stacking direction (vertical direction) of the first portion (FP of Kim ‘059) and the second portion (SP of Kim ‘059), a third size (third size as shown in annotated Fig 4 of Itaya ‘385) of each of the plurality of third portions (plurality of third portions of TSV1b disclosed in annotated Fig 4 of Itaya ‘385 as incorporated above) is less than a fourth size (fourth size as shown in annotated Fig 4 of Itaya ‘385) of the fourth portion (4P of Itaya ‘385 as incorporated above)(annotated Fig 4 of Itaya ‘385 discloses third size is less than fourth size).
With respect to Claim 10 Kim ‘059 as modified by Xi ‘363 and further modified by Itaya ‘385 discloses all limitations of the semiconductor device of claim 7, and Itaya ‘385 discloses further comprising:
a plurality of additional ring walls (additional ring walls 82 shown in Fig 4 of Itaya ‘385 and Para [0056]), and laterally surrounding (82 laterally surrounding plurality of third portions of TSV1b shown in Fig 4 of Itaya ‘385) the plurality of third portions (plurality of third portions of TSV1b disclosed in annotated Fig 4 of Itaya ‘385 as incorporated above),
wherein the fourth portion (4P) is vertically distant from (4P vertically distant from additional ring walls 82 shown in Fig 4 of Itaya ‘385) the plurality of additional ring walls (additional ring walls 82 shown in Fig 4 of Itaya ‘385).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Itaya ‘385’s further teaching of a plurality of additional ring walls, disposed inside the interconnect and laterally surrounding the plurality of third portions, wherein the fourth portion is vertically distant from the plurality of additional ring walls into Kim ‘059 as modified by Xi ‘363 and further modified by Itaya ‘385’s device. Itaya ‘385 teaches ring wall structures around the additional vertical interconnect structure. As these are identical structures to the first ring wall the person having ordinary skill in the art would have a reasonable expectation of success in adding the additional ring walls. Further, the ordinary artisan would have been motivated to further modify because providing the insulating ring outside the TSV (first portion) and the pad (second portion) the ring can provide protection against parasitic capacitance between the pad/TSV and adjacent devices as disclosed by Itaya ‘385 in Para [0010-0016 and 0056].
As incorporated, the teaching of additional ring walls (82) laterally surrounding third portions of the interconnects and vertically distant from fourth portions of the interconnects as taught by Itaya ‘385 would be used in device of Kim ‘059 as modified by Xi ‘363 and further modified by Itaya ‘385.
As incorporated, described above, (additional ring walls 82 of Itaya ‘385) are disposed inside the interconnect (103/104 of Kim ‘059).
With respect to Claim 11 Kim ‘059 as modified by Xi ‘363 and further modified by Itaya ‘385 discloses all limitations of the semiconductor device of claim 10, and Itaya ‘385 further discloses wherein in a vertical projection (Fig 4 of Itaya ‘385) along a stacking direction (stacking direction shown in annotated Fig 4 of Itaya ‘385) of the plurality of third portions (plurality of third portions of TSV1b disclosed in annotated Fig 4 of Itaya ‘385 as incorporated above) and the fourth portion (4P of Itaya ‘385 as incorporated above), each of the plurality of third portions (plurality of third portions of TSV1b disclosed in annotated Fig 4 of Itaya ‘385 as incorporated above) are confined by an innermost sidewall (innermost sidewall of 82 of Itaya ‘385 as incorporated above shown in annotated Fig 4 of Itaya ‘385) of a respective one of the plurality of additional ring walls (additional ring walls 82 shown in Fig 4 of Itaya ‘385), and the fourth portion (4P of Itaya ‘385 as incorporated above) is confined by a maximum distance (maximum distance shown in annotated Fig 4 of Itaya ‘385) between outermost sidewalls of the plurality of additional ring walls (additional ring walls 82 shown in Fig 4 of Itaya ‘385)(annotated Fig 4 of Itaya ‘385 discloses third portions are confined by an innermost sidewall of 82 and 4P is confined by a maximum distance between.
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Itaya ‘385’s further teaching of wherein in a vertical projection along a stacking direction of the plurality of third portions and the fourth portion, each of the plurality of third portions are confined by an innermost sidewall of a respective one of the plurality of additional ring walls, and the fourth portion is confined by a maximum distance between outermost sidewalls of the plurality of additional ring walls into Kim ‘059 as modified by Xi ‘363 and further modified by Itaya ‘385’s device. The ordinary artisan would have been motivated to modify Kim ‘059 as modified by Xi ‘363 and further modified by Itaya ‘385 in the manner set forth above, at least, because providing the insulating ring outside the TSV (first portion) and the pad (second portion) the ring can provide protection against parasitic capacitance between the pad/TSV and adjacent devices as disclosed by Itaya ‘385 in Para [0010-0016 and 0056].
As incorporated, the further teachings of Itaya ‘385 of third portions confined by an innermost ring wall and the fourth portion confined by a maximum distance between outermost ring walls would be used in the device of Kim ‘059 as modified by Xi ‘363 and further modified by Itaya ‘385.
With respect to Claim 12 Kim ‘059 as modified by Xi ‘363 and further modified by Itaya ‘385 discloses all limitations of the semiconductor device of claim 10, and Kim ‘059 as modified by Xi ‘363 and further modified by Itaya ‘385 discloses further wherein in a vertical projection (Fig 4 of Itaya ‘385) along a stacking direction (stacking direction as shown in annotated Fig 4 of Itaya ‘385) of the plurality of third portions (plurality of third portions of TSV1b disclosed in annotated Fig 4 of Itaya ‘385 as incorporated above) and the fourth portion (4P as incorporated above), each of the plurality of additional ring walls (additional ring walls 82 shown in Fig 4 of Itaya ‘385) has an annulus shape (82 having an annulus shape disclosed in Fig 6 of Itaya ‘385) continuously enclosing a respective third portion (left third portion of the plurality of third portions of TSV1b disclosed in annotated Fig 4 of Itaya ‘385 as incorporated above) of the plurality of third portions (plurality of third portions of TSV1b disclosed in annotated Fig 4 of Itaya ‘385 as incorporated above)(Fig 3 and 6 of Itaya ‘385 discloses 82 continuously enclosing 86 and 84 therefore the third portions are therefore continuously enclosed by 82).
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Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Farooq ‘487 in view of Xi ‘363 and in further view of Itaya ‘385, in view of the following arguments.
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With respect to Claim 14 Farooq ‘487 discloses a semiconductor device, comprising:
a substrate (substrate of 10, as shown in annotated Fig 11_2 of Farooq ‘487, Para [0027]);
an interconnect (32, Fig 1, Para [0029]), disposed over the substrate (10)(Fig 1 discloses 32 disposed over substrate);
a device layer (30, Fig 1, Para [0029], discloses FEOL components in layer 30), disposed between (30 disposed between substrate and 32 shown in Fig 1) the substrate (80) and the interconnect (32);
at least one first ring wall (24, Fig 3A and Fig 3B, Para [0036]), disposed inside (Fig 3B discloses 24 in 30) the device layer (30) over the substrate (substrate of 10) and further extending into the interconnect (32)(fig 3B discloses 24 extending into 32);
at least one first vertical connection structure (28, Fig 11, Para [0046]), embedded in (Fig 11 discloses 28 embedded in 32) and the interconnect (32) and penetrating through (Fig 11 discloses 28 penetrating substrate of 10) the substrate (substrate of 10), and comprising:
at least one first narrow portion (narrow portion of 28 as shown in annotated Fig 11_2 of Farooq ‘487), embedded inside the interconnect (32) and further extending into the substrate (substrate of 10)(annotated Fig 11_2 of Farooq ‘487 discloses narrow portion of 28 embedded inside 32 and further extending into the substrate); and
a first wide portion (wide portion 43/44 as shown in annotated Fig 11_2 of Farooq ‘487, Para [0046]), disposed in the substrate (substrate of 10) and exposed by the substrate (substrate of 10) (annotated Fig 11_2 of Farooq ‘487 discloses wide portion 43/44 is in substrate of 10 and is exposed by substrate of 10), the first wide portion (wide portion 43/44) being in contact with the at least one first narrow portion (narrow portion of 28)(annotated Fig 11_2 of Farooq ‘487 discloses 43/44 in contact with narrow portion 28),
Farooq ‘587 fails to explicitly disclose wherein an aspect ratio of the at least one first narrow portion is greater than an aspect ratio of the first wide portion; and
Nevertheless, in a related endeavor (Fig 1-8 of Xi ‘363), Xi ‘363 teaches wherein an aspect ratio of the second portion (202, Fig 8 of Xi ‘363, Para [0021]) is less than an aspect ratio of the first portion (210, Fig 8 of Xi ‘363, Para [0021]) (Para [0021] discloses aspect ratio of 202 as 1:1 and an aspect ratio of 210 as 4:1).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Xi ‘363’s teaching of an aspect ratio of the second portion is less than an aspect ratio of the first portion into Farooq ‘487’s device. Farooq ‘487 discloses a semiconductor device with a connection structure with a wider and shorter portion on top and a longer and narrower portion on the bottom but Farooq ‘487 does not disclose explicit dimensions or aspect ratios. Xi ‘363 teaches a semiconductor device with a connection structure with a wider and shorter upper portion and a longer and narrower lower portion and teaches that the upper portion has an aspect ratio that is less than the aspect ratio of the lower portion. The ordinary artisan would have been motivated to modify Farooq ‘487 in the manner set forth above, at least, because, as Xi ‘363 teaches in Para [0006] having an connection with a upper portion having a smaller aspect ratio than the lower portion of the connection structure provides less resistance in the structure. Further one of ordinary skill in the art would be motivated to have an upper bonding area with a larger diameter to aid in bonding additional contacts to the device.
As incorporated, the teaching of Xi ‘363 of an aspect ratio of the second portion is less than an aspect ratio of the first portion would be used as the relative aspect ratios of first portion (28) and second portion (43/44) of Farooq ‘487.
But Farooq ‘487 as modified by Xi ‘363 fails to explicitly disclose at least one first vertical connection structure electrically coupled to the interconnect; a metal feature, disposed over and electrically coupled to the at least one first vertical connection structure, the substrate being between the metal feature and the device layer.
Nevertheless in a related endeavor (Fig 1-22 of Itaya ‘385), Itaya ‘385 teaches at least one first vertical connection structure (TSV1, Fig 3 of Itaya ‘385, Para [0052]) electrically coupled to (Fig3 of Itaya ‘385 and Para [0053] discloses TSV1 electrically coupled to L0-L3) the interconnect (L0-L2, Fig 3 of Itaya ‘385, Para [0053]); a metal feature (P3, Fig 3 of Itaya ‘385, Para [0053]), disposed over and electrically coupled to (disclosed in Fig 3 of Itaya ‘385 and Para [0053]) the at least one first vertical connection structure (TSV1),
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Itaya ‘385’s teaching of at least one first vertical connection structure electrically coupled to the interconnect; a metal feature, disposed over and electrically coupled to the at least one first vertical connection structure, the substrate being between the metal feature and the device layer into Farooq ‘487 as modified by Xi ‘363’s device. Farooq ‘487 discloses a semiconductor device with a connection structure through a device layer, an interconnect layer and a substrate with a ring wall structure around the connection structure. Itaya ‘385 also teaches with a connection structure through a device layer, an interconnect layer and a substrate with a ring wall structure around the connection structure and Itaya ‘385 provides further details pertaining to connections on the device. The ordinary artisan would have been motivated to modify Farooq ‘487 as modified by Xi ‘363 in the manner set forth above, at least, because, the teachings of Itaya ‘385 provide the person of ordinary skill in the art information on forming their device with structures enabling connections to other devices, which would increase the functionality of the device.
As incorporated, the teaching of Itaya ‘385 of at least one first vertical connection structure (TSV1) electrically coupled to the interconnect (L0-L2); a metal feature (P3), disposed over and electrically coupled to the at least one first vertical connection structure (TSV1), would be used in the device of Farooq ‘487 as modified by Xi ‘363 such that vertical connection (28) would be electrically coupled to interconnect (32) and metal feature (P3 of Itaya ‘385) would be disposed over and electrically coupled to vertical connection (28) of Farooq ‘487 as modified by Xi ‘363.
As incorporated, the substrate (substrate of 10 of Farooq ‘487) being between the metal feature (P3 of Itaya ‘385 as incorporated above) and the device layer (30 of Farooq ‘587)(as incorporated metal feature P3 of Itaya ‘385 is over 43/44 of Farooq ‘487, therefore substrate of 10 is between P3 and 30).
With respect to Claim 15 Farooq ‘487 as modified by Xi ‘363 and further modified by Itaya ‘385 discloses all limitations of the semiconductor device of claim 14, and Itaya ‘385 further discloses wherein the at least one first narrow portion (first narrow portion of TSV1, as shown in annotated Fig 4_2 of Itaya ‘385, Para [0056]) comprises a plurality of first narrow portions laterally arranged next to one another (annotated Fig 4_2 of Itaya ‘385 and Para [0056] discloses a plurality of first narrow portions laterally arranged next to one another), and the at least one first ring wall (82, Fig 4_2 of Itaya ‘385, Para [0056]) comprises a plurality of first ring walls respectively surrounding and spacing apart from the plurality of first narrow portions (annotated Fig 4_2 of Itaya ‘385 discloses a plurality of first ring walls 82 surrounding and spacing apart from plurality of first narrow portions of TSV1),
wherein the first wide portion (84, Fig 4, Para [0058]) is spacing apart from the plurality of first ring walls (82) and electrically coupled (Fig 4 and Para [0058] disclose 84 electrically coupled to TSV1, therefore to the plurality of first narrow portions of TSV1) to the plurality of first narrow portions (first narrow portion of TSV1).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Itaya ‘385’s further teaching of wherein the at least one first narrow portion comprises a plurality of first narrow portions laterally arranged next to one another, and the at least one first ring wall comprises a plurality of first ring walls respectively surrounding and spacing apart from the plurality of first narrow portions, wherein the first wide portion is spacing apart from the plurality of first ring walls and electrically coupled to the plurality of first narrow portions into Farooq ‘487 as modified by Xi ‘363 and further modified by Itaya ‘385’s device. The ordinary artisan would have been motivated to further modify Farooq ‘487 as modified by Xi ‘363 and further modified by Itaya ‘385 in the manner set forth above, at least, because Itaya ‘385 teaches that the ring wall formed in this structure, providing the insulating ring outside the TSV (first portion) and the pad (second portion), that the ring can provide protection against parasitic capacitance between the pad/TSV and adjacent devices as disclosed by Itaya ‘385 in Para [0010-0016 and 0056]..
As incorporated, the above arrangements of the ring wall and connection portions taught by Itaya ‘385 would be incorporated in the ring wall and connections of Farooq ‘487 as modified by Xi ‘363 and further modified by Itaya ‘385.
With respect to Claim 16 Farooq ‘487 as modified by Xi ‘363 and further modified by Itaya ‘385 discloses all limitations of the semiconductor device of claim 14, and Itaya ‘385 discloses further comprising:
a bonding layer (L3, Fig 4, Para [0059]), disposed on and electrically coupled (L3 on and electrically coupled to TSV1 disclosed in Fig 4 and Para [0058] of Itaya ‘385) the at least one first vertical connection structure (TSV1 of Itaya ‘385 as incorporated above), wherein the metal feature (P3 of Itaya ‘385 as incorporated above) is included in the bonding layer (Fig 4 of Itaya ‘385 discloses P3 included in L3); or
an additional interconnect, disposed on and electrically coupled the at least one first vertical connection structure, wherein the metal feature is included in the additional interconnect.
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Itaya ‘385’s further teaching of a bonding layer, disposed on and electrically coupled the at least one first vertical connection structure, the substrate being between the bonding layer and the device layer, wherein the metal feature is included in the bonding layer into Farooq ‘487 as modified by Xi ‘363 and further modified by Itaya ‘385’s device. The ordinary artisan would have been motivated to further modify Farooq ‘487 as modified by Xi ‘363 and further modified by Itaya ‘385 in the manner set forth above, at least, because the teachings of Itaya ‘385 provide the person of ordinary skill in the art information on forming their device with structures enabling connections to other devices, which would increase the functionality of the device.
As incorporated, the further teaching of Itaya ‘385 of a bonding layer (L3), disposed on and electrically coupled the at least one first vertical connection structure (TSV1), the substrate being between the bonding layer and the device layer, wherein the metal feature (P3) is included in the bonding layer; would be used in device of Farooq ‘487 as modified by Xi ‘363 and further modified by Itaya ‘385.
As incorporated in the above description, Farooq ‘487 as modified by Xi ‘363 and further modified by Itaya ‘385 the substrate (substrate of 10 of Farooq ‘487) being between the bonding layer (L3 of Itaya ‘385 as incorporated above) and the device layer (30 of Farooq ‘487) and the substrate (substrate of 10 of Farooq ‘487) being between the additional interconnect (85 of Itaya ‘385 as incorporated above) and the device layer (30 of Farooq ‘487)(as incorporated in the description above the bonding layer L3 of Itaya ‘385 and additional interconnect 85 of Itaya ‘385 would be above wide portion 43/44 of Farooq ‘487, therefore the substrate would be between L3 and 30 and between 85 and 30).
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With respect to Claim 17 Farooq ‘487 as modified by Xi ‘363 and further modified by Itaya ‘385 discloses all limitations of the semiconductor device of claim 14, and Itaya ‘385 discloses further comprising:
at least one second vertical connection structure (TSV1b, Fig 4 of Itaya ‘385, Para [0056]), embedded in the interconnect (81, Fig 4 of Itaya ‘385, Para [0031]) and penetrating through (Fig 4 of Itaya ‘385 discloses TSV1b embedded in 81 and penetrating 80) the substrate (80, Fig 4 of Itaya ‘385, Para [0052]), the at least one second vertical connection structure (TSV1b) being laterally next to (shown in Fig 4 of Itaya ‘385) the at least one first vertical connection structure (TSV1a, Fig 4 of Itaya ‘385, Para [0056]), and comprising:
a plurality of second narrow portions (plurality of second narrow portions of TSV1b shown in annotated Fig 4_2 of Itaya ‘385), embedded inside the interconnect (81) and further extending into the substrate (80) (annotated Fig 4_2 of Itaya ‘385 discloses plurality of second narrow portions of TSV1b embedded in 81 and extending into 80); and
a second wide portion (second wide portion of TSV1b shown in annotated Fig 4_2 of Itaya ‘385), disposed in the substrate (80) and exposed by the substrate (annotated Fig 4_2 of Itaya ‘385 discloses exposing second wide portion), the second wide portion (second wide portion of TSV1b shown in annotated Fig 4_2 of Itaya ‘385) being in contact with the plurality of second narrow portions (plurality of second narrow portions of TSV1b shown in annotated Fig 4_2 of Itaya ‘385)(annotated Fig 4_2 of Itaya ‘385 discloses second wide portion in contact with plurality of second narrow portions),
wherein an aspect ratio (height:width) of each of the plurality of second narrow portions (plurality of second narrow portions of TSV1b shown in annotated Fig 4_2 of Itaya ‘385) is greater than an aspect ratio (height:width) of the second wide portion (second wide portion of TSV1b shown in annotated Fig 4_2 of Itaya ‘385) (annotated Fig 4_2 of Itaya ‘385 discloses height:width of plurality of second narrow portions of TSV1b is greater than height:width of (second wide portion of TSV1b).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Itaya ‘385’s further teaching of at least one second vertical connection structure, embedded in and electrically coupled to the interconnect and penetrating through the substrate, the at least one second vertical connection structure being laterally next to the at least one first vertical connection structure, and comprising: a plurality of second narrow portions, embedded inside the interconnect and further extending into the substrate; and a second wide portion, disposed in the substrate and exposed by the substrate, the second wide portion being in contact with the plurality of second narrow portions, wherein an aspect ratio of each of the plurality of second narrow portions is greater than an aspect ratio of the second wide portion into Farooq ‘487 as modified by Xi ‘363 and further modified by Itaya ‘385’s device. The ordinary artisan would have been motivated to further modify Farooq ‘487 as modified by Xi ‘363 and further modified by Itaya ‘385 in the manner set forth above, at least, because providing the second vertical connection structure in can provide additional functionality to the device.
As incorporated, the second vertical connection structure (TSV1b) with the structure described above taught by Itaya ‘385 would be used in the device of Farooq ‘487 as modified by Xi ‘363 and further modified by Itaya ‘385.
As incorporated, described above, the at least one second vertical connection structure (TSV1b of Itaya ‘385 as incorporated above) would be embedded in and electrically coupled to interconnect (32) of Farooq ‘487 as modified by Xi ‘363 and further modified by Itaya ‘385.
Conclusion
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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