DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3-9, & 11-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 9613949) [Hereinafter Chen] & Chen et al. (US 9368484) [Hereinafter Chen_2016].
Regarding claim 1, Chen teaches A semiconductor device, comprising:
a semiconductor substrate [fig. 2, substrate 10, para 8] having a first conductivity type [para 8; p-type, “the semiconductor substrate 10 may be a second conductivity type substrate, such as a p-type substrate, but the present invention is not limited to this.”];
a well region [fig. 2, well W2, para 8 “The second conductivity type well W2 is disposed in the third region R3.”] having the first conductivity type [para 8, p-type] in the semiconductor substrate [fig 2];
a fin [fig. 2, fin F3, para 7] disposed on the semiconductor substrate within the well region (fig. 2, W2),
wherein the fin (fig. 2, F3) extends along a first direction [fig. 2, horizontal D1),
wherein the fin (fig. 2, F3) comprises a first portion [annotated fig. 2] and a second portion [annotated fig. 2] that is contiguous with the first portion.
Chen fails to explicitly disclose wherein the first portion comprises a counter-doping region having dopants of a second conductivity type; and
a gate extending over the fin along a second direction,
wherein the gate overlaps with the first portion of the fin and does not overlap with the second portion of the fin.
However, Chen_2016 teaches wherein the first portion [fig. 6, third part 21B, para 20] comprises a counter-doping region having dopants of a second conductivity type [para 20, “The third part 21B of the first fin 21 may be a second conductivity type part a lightly doped first conductivity type part, or a non-doped part, but not limited thereto.”]; and
a gate [fig. 6, gate structure 40, para 20] extending over the fin [fig. 6, 21, para 20] along a second direction [fig. 6, vertical direction D3],
wherein the gate (fig. 6, gate 40) overlaps with the first portion of the fin (fig. 6, 21B) and does not overlap with the second portion (fig. 6, first part 21A, para 20] of the fin (fig. 6, 21).
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the gate structure to extend and overlap a portion of the fin thereby enhancing electrostatic control and enabling efficient charge diversion which enhances ESD robustness.
PNG
media_image1.png
712
1149
media_image1.png
Greyscale
Chen, ANNOTATED FIG. 2
Regarding claim 3 Chen/Chen_2016 teaches The semiconductor device according to claim 1,
wherein the second portion of the fin [Chen_2016, fig. 6, 21A, para 20] does not include the dopants of the second conductivity type [Chen_2016, fig. 2, para 20; wherein the first portion 21B is a second conductivity “The third part 21B of the first fin 21 may be a second conductivity type part.” And the second portion 21A is a first conductivity type “a first part 21A having a first conductivity type”].
Regarding claim 4 Chen/Chen_2016 teaches The semiconductor device according to claim 1,
wherein the first conductivity type is P type and the second conductivity type is N type [Chen, para 8, “the first conductivity type may be n-type as the second conductivity type is p-type, or the first conductivity type may be p-type as the second conductivity type is n-type.”].
Regarding claim 5, Chen/Chen_2016 teaches The semiconductor device according to claim 1,
wherein the well region is a P well region [Chen, fig. 2, well W2, para 8 “The second conductivity type well W2 is disposed in the third region R3.”], and
wherein the first portion of the fin and the second portion of the fin are above the P well region. [Chen, annotated fig. 2; wherein the first and second portions of the fin are above the P-well region W2].
Regarding claim 6, Chen/Chen_2016 teaches The semiconductor device according to claim 1,
wherein the second portion [Chen, annotated fig. 2] of the fin comprises an epitaxial layer [Chen, fig. 2, epitaxial structure 63, para 14].
Regarding claim 7, Chen/Chen_2016 teaches The semiconductor device according to claim 6,
wherein the epitaxial layer comprises a SiP epitaxial layer [para 9 states, “epitaxial material of the first epitaxial structures 61 may include . . . silicon phosphorus (SiP).” Furthermore para 14 states, “Therefore, the third epitaxial structure 63 may be formed by the process of forming the first epitaxial structure 61”].
Regarding claim 8, Chen teaches The semiconductor device according to claim 6,
wherein the epitaxial layer [Chen, fig. 2, epitaxial structure 63, para 14] is contiguous with the region in the first portion of the fin [Chen, fig. 2, annotated fig. 2].
Chen fails to explicitly disclose wherein the region in the first portion of the fin is a counter-doping region.
However, Chen_2016 teaches wherein the first portion [fig. 6, third part 21B, para 20] comprises a counter-doping region [para 20, “The third part 21B of the first fin 21 may be a second conductivity type part a lightly doped first conductivity type part, or a non-doped part, but not limited thereto.”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the epitaxial portion of the fin being contiguous with the counter-doping portion of the fin to enhance ESD robustness by providing a superior heat sink and lowering contact resistance to prevent thermal failure.
Regarding claim 9, Chen/Chen_2016 teaches The semiconductor device according to claim 1,
wherein the gate is a metal gate [Chen_2016, fig. 6, gate structure 40, para 19, “The gate structure 40 may include a metal gate structure”].
Regarding claim 11, Chen teaches A semiconductor device, comprising:
a semiconductor substrate [fig. 2, substrate 10, para 8] having a first conductivity type [para 8; p-type, “the semiconductor substrate 10 may be a second conductivity type substrate, such as a p-type substrate, but the present invention is not limited to this.”];
a well region [fig. 2, well W2, para 8 “The second conductivity type well W2 is disposed in the third region R3.”] having the first conductivity type [para 8, p-type] in the semiconductor substrate [fig 2];
a fin [fig. 2, fin F3, para 7] disposed on the semiconductor substrate within the well region (fig. 2, W2),
wherein the fin (fig. 2, F3) extends along a first direction [fig. 2, horizontal D1),
wherein the fin (fig. 2, F3) comprises a first portion [annotated fig. 2] and a second portion [annotated fig. 2] that is contiguous with the first portion,
Chen fails to explicitly disclose wherein the first portion comprises a counter-doping region having dopants of a second conductivity type; and
a gate extending over the fin along a second direction,
wherein the gate overlaps with the first portion of the fin and does not overlap with the second portion of the fin.
However, Chen_2016 teaches wherein the first portion [fig. 6, third part 21B, para 20] comprises a counter-doping region having dopants of a second conductivity type [para 20, “The third part 21B of the first fin 21 may be a second conductivity type part a lightly doped first conductivity type part, or a non-doped part, but not limited thereto.”]; and
a gate [fig. 6, gate structure 40, para 20] extending over the fin [fig. 6, 21, para 20] along a second direction [fig. 6, vertical direction D3],
wherein the gate (fig. 6, gate 40) overlaps with the first portion of the fin (fig. 6, 21B) and does not overlap with the second portion (fig. 6, first part 21A, para 20] of the fin (fig. 6, 21).
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the gate structure to extend and overlap a portion of the fin thereby enhancing electrostatic control and enabling efficient charge diversion which enhances ESD robustness.
Regarding claim 12, Chen/Chen_2016 teaches The semiconductor device according to claim 11.
Chen/Chen_2016 fails to explicitly disclose an insulating layer disposed between the first portion of the fin and the gate,
wherein the gate, the first portion, and the insulating layer constitute a metal-oxide-semiconductor capacitor.
Chiang teaches an insulating layer [fig. 2, gate dielectric layer 211, para 26] disposed between the first portion of the fin [fig. 2, fin 101, para 26] and the gate [fig. 2, gate 213, para 26],
wherein the gate, the first portion, and the insulating layer constitute a metal-oxide-semiconductor capacitor [fig. 2, wherein the gate 213, dielectric layer 211 placed on the a silicon substrate forms a metal oxide semiconductor capacitor].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the gate, gate dielectric, and fin to form a metal oxide capacitor to minimize short channel effects, reduce leakage current, and improve switching speed.
Regarding claim 13 Chen/Chen_2016 teaches The semiconductor device according to claim 11,
wherein the second portion of the fin [Chen_2016, fig. 6, 21A, para 20] does not include the dopants of the second conductivity type [Chen_2016, fig. 2, para 20; wherein the first portion 21B is a second conductivity “The third part 21B of the first fin 21 may be a second conductivity type part.” And the second portion 21A is a first conductivity type “a first part 21A having a first conductivity type”].
Regarding claim 14 Chen/Chen_2016 teaches The semiconductor device according to claim 11,
wherein the first conductivity type is P type and the second conductivity type is N type [Chen, para 8, “the first conductivity type may be n-type as the second conductivity type is p-type, or the first conductivity type may be p-type as the second conductivity type is n-type.”].
Regarding claim 15, Chen/Chen_2016 teaches The semiconductor device according to claim 11,
wherein the fin is surrounded by a trench isolation structure [Chen annotated fig. 2], and
wherein the first portion of the fin and the second portion of the fin are above the trench isolation structure [Chen, annotated fig. 2].
Regarding claim 16, Chen/Chen_2016 teaches The semiconductor device according to claim 11,
wherein the second portion [Chen, annotated fig. 2] of the fin comprises an epitaxial layer [Chen, fig. 2, epitaxial structure 63, para 14].
Regarding claim 17, Chen/Chen_2016 teaches The semiconductor device according to claim 16,
wherein the epitaxial layer comprises a SiP epitaxial layer [para 9 states, “epitaxial material of the first epitaxial structures 61 may include . . . silicon phosphorus (SiP).” Furthermore para 14 states, “Therefore, the third epitaxial structure 63 may be formed by the process of forming the first epitaxial structure 61”].
Regarding claim 18, Chen teaches The semiconductor device according to claim 16,
wherein the epitaxial layer [Chen, fig. 2, epitaxial structure 63, para 14] is contiguous with the region in the first portion of the fin [Chen, fig. 2, annotated fig. 2].
Chen fails to explicitly disclose wherein the region in the first portion of the fin is a counter-doping region.
However, Chen_2016 teaches wherein the first portion [fig. 6, third part 21B, para 20] comprises a counter-doping region [para 20, “The third part 21B of the first fin 21 may be a second conductivity type part a lightly doped first conductivity type part, or a non-doped part, but not limited thereto.”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the epitaxial portion of the fin being contiguous with the counter-doping portion of the fin to enhance ESD robustness by providing a superior heat sink and lowering contact resistance to prevent thermal failure.
Regarding claim 19, Chen/Chen_2016 teaches The semiconductor device according to claim 11,
wherein the gate is a metal gate [Chen_2016, fig. 6, gate structure 40, para 19, “The gate structure 40 may include a metal gate structure”].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chen & Chen_2016 as applied to claims 1, 3-9, & 11-19 and further in view of Chiang et al. (US 2020/0126978) [Hereinafter Chiang].
Regarding claim 2, Chen/Chen_2016 teaches The semiconductor device according to claim 1.
Chen/Chen_2016 fails to explicitly disclose an insulating layer disposed between the first portion of the fin and the gate,
wherein the gate, the first portion, and the insulating layer constitute a metal-oxide-semiconductor capacitor.
Chiang teaches an insulating layer [fig. 2, gate dielectric layer 211, para 26] disposed between the first portion of the fin [fig. 2, fin 101, para 26] and the gate [fig. 2, gate 213, para 26],
wherein the gate, the first portion, and the insulating layer constitute a metal-oxide-semiconductor capacitor [fig. 2, wherein the gate 213, dielectric layer 211 placed on the a silicon substrate forms a metal oxide semiconductor capacitor].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the gate, gate dielectric, and fin to form a metal oxide capacitor to minimize short channel effects, reduce leakage current, and improve switching speed.
Claim(s) 10 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen & Chen_2016 as applied to claims 1, 3-9, & 11-19 and further in view of Nidhi et al. (US 2021/0183850) [Hereinafter Nidhi].
Regarding claim 10, Chen/Chen_2016 teaches The semiconductor device according to claim 1.
Chen/Chen_2016 fails to explicitly disclose wherein the counter-doping region has a doping concentration of 1.5×1018-1.5×1020 atoms/cm3.
While Chen_2016 notes the counter-doping region [fig. 6, third part 21B, para 20, “The third part 21B of the first fin 21 may be a second conductivity type part a lightly doped first conductivity type part, or a non-doped part, but not limited thereto.”].
Nidhi further teaches an analogous ESD solution for fin-based devices wherein an n-type doping region [fig. 4I, first region 410A, para 60] has a doping concentration of “1019 cm−3 or less, or between approximately 1017 cm−3 and 1019 cm−3.
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the doping concentration of the counter-doping region to carry a doping concentration of “1019 cm−3 or less, or between approximately 1017 cm−3 and 1019 cm−3.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.
Regarding claim 20, Chen/Chen_2016 teaches The semiconductor device according to claim 11.
Chen/Chen_2016 fails to explicitly disclose wherein the counter-doping region has a doping concentration of 1.5×1018-1.5×1020 atoms/cm3.
While Chen_2016 notes the counter-doping region [fig. 6, third part 21B, para 20, “The third part 21B of the first fin 21 may be a second conductivity type part a lightly doped first conductivity type part, or a non-doped part, but not limited thereto.”].
Nidhi further teaches an analogous ESD solution for fin-based devices wherein an n-type doping region [fig. 4I, first region 410A, para 60] has a doping concentration of “1019 cm−3 or less, or between approximately 1017 cm−3 and 1019 cm−3.
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the doping concentration of the counter-doping region to carry a doping concentration of “1019 cm−3 or less, or between approximately 1017 cm−3 and 1019 cm−3.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FELIX B ANDREWS whose telephone number is (703)756-1074. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FELIX B ANDREWS/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812