DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5, 9-15, & 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 2015/0279933) [Hereinafter Xiao] & Hu et al. (US 2013/0328162) [Hereinafter Hu].
Regarding claim 1, Xiao teaches A semiconductor device, comprising:
a semiconductor substrate [fig. 2B, substrate 110, para 39].
a well region [fig. 2B, active region 114, para 41] having the first conductivity type [p-type] in the semiconductor substrate (fig. 2B, 110);
a fin [fig. 2B, body 120, 41] disposed on the semiconductor substrate (fig. 2B, 110),
wherein the fin (fig. 2, 120) extends along a first direction.
wherein the fin [fig. 1, semiconductor body 120, para 45] comprises
a first portion [fig. 2B, channel region 128, para 45] and two second portions [fig. 2B, source region 124 & drain region 126, para 45] that are at two ends of the first portion and contiguous with the first portion [fig. 2B],
wherein the first portion and the two second portions have a second conductivity type [para 10],
the first portion (fig. 2B, 128) comprises a counter-doping region having dopants of the second conductivity type [fig. 2B; wherein the channel region is n-doped on top of P-type active region],
wherein a cross-sectional profile of the first portion of the fin is different from cross-sectional profiles of the two second portions of the fin [fig. 2B]; and
a gate [fig. 2B, gate electrode 132, para 52] extending over the fin along a second direction [fig. 2B],
wherein the gate (fig. 2B, 132) overlaps with the first portion of the fin (fig. 2B, 128) and does not overlap with the two second portions of the fin (fig. 2B, 124 & 126).
Xiao fails to explicitly disclose a semiconductor substrate having a first conductivity type;
a fin disposed on the semiconductor substrate within the well region.
Hu teaches a semiconductor substrate [fig. 1B, substrate 101, para 18] having a first conductivity type [p-type];
a fin [fig. 1B, fin 120, para 16] disposed on the semiconductor substrate (fig. 1B, 101) within the well region [fig. 1B, p-well 107, para 18].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the substrate to be doped and the fins to be within a well region to isolate the transistors and control threshold voltages.
Regarding claim 2, Xiao/Hu teaches The semiconductor device according to claim 1 further comprising:
an insulating layer [Xiao, fig. 2B, gate dielectric 130, para 49] disposed between the first portion of the fin (Xiao, fig. 2B, 128) and the gate (Xiao, fig. 2B, 132),
wherein the gate, the first portion, and the insulating layer constitute a metal-oxide-semiconductor capacitor [fig. 2B, wherein the gate 130, dielectric layer 132 placed on a silicon substrate 110 forms a metal oxide semiconductor capacitor].
Regarding claim 3, Xiao/Hu teaches the semiconductor device according to claim 1,
wherein the two second portions of the fin do not include the counter-doping region [Xiao, para 11].
Regarding claim 4, Xiao/Hu teaches The semiconductor device according to claim 1,
wherein the first conductivity type is P type and the second conductivity type is N type [Xiao, para 11 & claim 16; wherein the first and second conductivity type can be either P-type or N-type as desired by design].
Regarding claim 5, Xiao/Hu teaches The semiconductor device according to claim 1,
wherein the well region is a P well region [Xiao, fig. 2, active region 114, para 40] and
wherein the first portion of the fin and the two second portions of the fin are above the P well region [Xiao, fig. 2].
Regarding claim 9, Xiao/Hu teaches The semiconductor device according to claim 1,
wherein the gate is a metal gate [Xiao, fig. 2B, 132, para 49].
Regarding claim 10, Xiao/Hu teaches The semiconductor device according to claim 1,
wherein the counter-doping region has a concentration of 1.5 x 1018 – 1.5 x 1020 atoms/cm3 [Xiao, fig. 3A, para 30-31 teaches the concentration of the counter-doping region (channel region) which overlaps the range claimed].
Regarding claim 11, Xiao teaches A semiconductor device, comprising:
a semiconductor substrate [fig. 2B, substrate 110, para 39];
a fin [fig. 2B, body 120, 41] disposed on the semiconductor substrate (fig. 2B, 110),
wherein the fin (fig. 2, 120) extends along a first direction.
wherein the fin [fig. 1, semiconductor body 120, para 45] comprises
a first portion [fig. 2B, channel region 128, para 45] and two second portions [fig. 2B, source region 124 & drain region 126, para 45] that are at two ends of the first portion and contiguous with the first portion [fig. 2B],
wherein the first portion and the two second portions have a second conductivity type [para 10],
the first portion (fig. 2B, 128) comprises a counter-doping region having dopants of the second conductivity type [fig. 2B; wherein the channel region is n-doped on top of P-type active region],
wherein a cross-sectional profile of the first portion of the fin is different from cross-sectional profiles of the two second portions of the fin [fig. 2B]; and
a gate [fig. 2B, gate electrode 132, para 52] extending over the fin along a second direction [fig. 2B],
wherein the gate (fig. 2B, 132) overlaps with the first portion of the fin (fig. 2B, 128) and does not overlap with the two second portions of the fin (fig. 2B, 124 & 126).
Hu teaches a semiconductor substrate [fig. 1B, substrate 101, para 18] having a first conductivity type [p-type].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the substrate to be doped and the fins to be within a well region to isolate the transistors and control threshold voltages.
Regarding claim 12, Xiao/Hu teaches The semiconductor device according to claim 11 further comprising:
an insulating layer [Xiao, fig. 2B, gate dielectric 130, para 49] disposed between the first portion of the fin (Xiao, fig. 2B, 128) and the gate (Xiao, fig. 2B, 132),
wherein the gate, the first portion, and the insulating layer constitute a metal-oxide-semiconductor capacitor [fig. 2B, wherein the gate 130, dielectric layer 132 placed on a silicon substrate 110 forms a metal oxide semiconductor capacitor].
Regarding claim 13, Xiao/Hu teaches The semiconductor device according to claim 11,
wherein the two second portions of the fin do not include the counter-doping region [Xiao, para 11].
Regarding claim 14, Xiao/Hu teaches The semiconductor device according to claim 11,
wherein the first conductivity type is P type and the second conductivity type is N type [Xiao, para 11 & claim 16; wherein the first and second conductivity type can be either P-type or N-type as desired by design].
Regarding claim 15, Xiao/Hu teaches The semiconductor device according to claim 11,
wherein the fin [Hu, fig. 1B, fin 120] is surrounded by a trench isolation structure [Hu, fig. 1B, STI features 121, para 19], and
wherein the first portion of the fin [Xiao, fig. 2B, 128] and the two second portions of the fin [Xiao, fig. 2B, 124/126] are above the trench isolation structure [Xu, fig. 2B, isolation region 112].
Regarding claim 19, Xiao/Hu teaches The semiconductor device according to claim 11,
wherein the gate is a metal gate [Xiao, fig. 2B, 132, para 49].
Regarding claim 20, Xiao/Hu teaches The semiconductor device according to claim 11,
wherein the counter-doping region has a doping concentration of 1.5x1018-1.5x1020 atoms/cm3 [Xiao, fig. 3A, para 30-31 teaches the concentration of the counter-doping region (channel region) which overlaps the range claimed].
Claim(s) 6-7 & 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao & Hu as applied to claims 1-5, 9-15, & 19-20 and further in view of Wu et al. (US 2017/0345828).
Regarding claim 6, Xiao/Hu teaches The semiconductor device according to claim 1.
Xiao/Hu fails to explicitly disclose wherein the two second portions of the fin respectively comprise an epitaxial layer.
Wu teaches wherein the two second portions of the fin respectively comprise an epitaxial layer [para 19, “The fin structure 140 may be a P well over a silicon substrate, and the source regions S1 to S4, the drain regions D1 to D4 and the source/drain regions SA and SB may be elevated and formed on the fin structure 140 by an epitaxial silicon phosphorous (SiP). . .”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the second portions (source and drain regions) to comprise epitaxial regions reducing contact resistance and eliminate crystal damage from ion implantation.
Regarding claim 7, Xiao/Hu/Wu teaches The semiconductor device according to claim 6,
wherein the epitaxial layer comprises a SiP epitaxial layer [Wu, para 19, “The fin structure 140 may be a P well over a silicon substrate, and the source regions S1 to S4, the drain regions D1 to D4 and the source/drain regions SA and SB may be elevated and formed on the fin structure 140 by an epitaxial silicon phosphorous (SiP). . .”].
Regarding claim 8, Xiao/Hu/Wu teaches The semiconductor device according to claim 6,
wherein the epitaxial layer is contiguous with the counter-doping region in the first portion of the fin. [Wu teaches the source/drain to be formed utilizing an epitaxial process. Xiao teaches the source/drain contiguous with the first portion (channel region)].
Regarding claim 16, Xiao/Hu teaches The semiconductor device according to claim 11.
Xiao/Hu fails to explicitly disclose wherein the two second portions of the fin respectively comprise an epitaxial layer.
Wu teaches wherein the two second portions of the fin respectively comprise an epitaxial layer [para 19, “The fin structure 140 may be a P well over a silicon substrate, and the source regions S1 to S4, the drain regions D1 to D4 and the source/drain regions SA and SB may be elevated and formed on the fin structure 140 by an epitaxial silicon phosphorous (SiP). . .”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the second portions (source and drain regions) to comprise epitaxial regions reducing contact resistance and eliminate crystal damage from ion implantation.
Regarding claim 17, Xiao/Hu/Wu teaches The semiconductor device according to claim 16,
wherein the epitaxial layer comprises a SiP epitaxial layer [Wu, para 19, “The fin structure 140 may be a P well over a silicon substrate, and the source regions S1 to S4, the drain regions D1 to D4 and the source/drain regions SA and SB may be elevated and formed on the fin structure 140 by an epitaxial silicon phosphorous (SiP). . .”].
Regarding claim 18, Xio/Hu/Wu teaches The semiconductor device according to claim 16,
wherein the epitaxial layer is contiguous with the counter-doping region in the first portion of the fin [Wu teaches the source/drain to be formed utilizing an epitaxial process. Xiao teaches the source/drain contiguous with the first portion (channel region)].
Conclusion
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/FELIX B ANDREWS/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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