DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II (claims 8-27) in the reply filed on May 05th, 2026 is acknowledged. Non-elected claims 1-7 have been cancelled by the Application.
Information Disclosure Statement
The IDS filed on January 03rd, 2024 has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Method of forming a semiconductor device by performing an implantation process to implant a dopant into a bottom portion of a dielectric layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-10, 14, 15, and 21-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (U.S. Pub. 2023/0378264) in view of Li et al. (U.S. Pub. 2017/0358663).
In re claim 8, Song discloses a method, comprising forming a sacrificial gate stack (DG1,DG2) over a portion of a fin structure (see paragraph [0110] and fig. 22); removing an exposed portion of the fin structure to expose a portion of a substrate 100 and a surface of a semiconductor layer (BNW1,BNW2) of the fin structure (see paragraph [0030] and fig. 22); depositing a first semiconductor material BSD on the exposed portion of the substrate 100; depositing a dielectric layer 130, wherein the dielectric layer 130 comprises a bottom portion disposed on the first semiconductor material BSD and a sidewall portion disposed on the surface of the semiconductor layer (see paragraph [0065] and fig. 23); removing the sidewall portion of the dielectric layer 130 (see paragraphs [0065], [0066] and fig. 23); and forming a second semiconductor material USD on the bottom portion of the dielectric layer 130 (see paragraph [0067] and fig. 23).
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Song is silent to performing an implantation process to implant a dopant in the bottom portion of the dielectric layer; then performing an annealing process on the bottom portion of the dielectric layer.
However, Li discloses in a same field of endeavor, a method of forming a semiconductor device, including, inter-alia, a step of performing an implantation process to implant a dopant (such as Si, B, P, He, or Ge) in the bottom portion of the dielectric layer; then performing an annealing process on the bottom portion of the dielectric layer in order to improve film quality, including strengthening the film and improve the film density and hardness (see paragraph [0070]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Li into the method of Song in order to enable the process of performing an implantation process to implant a dopant in the bottom portion of the dielectric layer; then performing an annealing process on the bottom portion of the dielectric layer in Song to be performed in order to improve film quality, including strengthening the film and improve the film density and hardness (see paragraph [0070] of Li). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 9, as applied to claim 8 above, Song discloses wherein a dopant concentration of the dielectric layer ranges from about 1 x 1014 to 5x1016 cm-2 (see paragraph [0073]) but is silent to wherein a dopant concentration of the dielectric layer ranges from about 5 X 10²⁰ cm⁻³ to about 1 X 10²¹ cm⁻³.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art to optimize the dopant concentration ranges in the dielectric layer during routine experimentation to be about 5 X 10²⁰ cm⁻³ to about 1 X 10²¹ cm⁻³ since where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See in re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
In re claim 10, as applied to claim 8 above, Song in combination with Li discloses wherein the implantation process implants the dopant in gate spacers formed along sidewalls of the sacrificial gate stack (see paragraph [0070] of Li).
In re claim 14, as applied to claim 8 above, Song in combination with Li discloses wherein the bottom portion of the dielectric layer 130 has a center portion having a first thickness and an edge portion having a second thickness substantially less than the first thickness (see paragraph [0065] and fig. 23 of Song).
In re claim 15, as applied to claim 14 above, Song in combination with Li discloses wherein the method further comprising a wet clean process after the annealing process and before the forming the second semiconductor material (see paragraphs [0075], [0077] of Li). Song and Li are silent to wherein the first thickness of the bottom portion of the dielectric layer ranges from about 2 nm to about 5 nm after the wet clean process.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art to optimize the first thickness of the bottom portion of the dielectric layer to be in a ranges from about 2 nm to about 5 nm during routine experimentation since where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See in re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
In re claim 21, Song discloses a method, comprising forming a sacrificial gate stack (DG1,DG2) over a portion of a fin structure; removing an exposed portion of the fin structure to expose a portion of a substrate 100 (see paragraph [0110] and fig. 23); depositing a first semiconductor material BSD on the exposed portion of the substrate 100; forming a dielectric layer 130 on the first semiconductor material BSD; and forming a second semiconductor material USD on the dielectric layer 130 (see paragraphs [0064], [0067] and fig. 23).
Song is silent to the step of performing an implantation process to implant a dopant in the dielectric layer; performing an annealing process on the dielectric layer.
However, Li discloses in a same field of endeavor, a method of forming a semiconductor device, including, inter-alia, a step of performing an implantation process to implant a dopant (such as Si, B, P, He, or Ge) in the dielectric layer; then performing an annealing process on the dielectric layer in order to improve film quality, including strengthening the film and improve the film density and hardness (see paragraph [0070]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Li into the method of Song in order to enable the process of performing an implantation process to implant a dopant in the dielectric layer; performing an annealing process on the dielectric layer in Song to be performed in order to improve film quality, including strengthening the film and improve the film density and hardness (see paragraph [0070] of Li). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 22, as applied to claim 21 above, Song in combination with Li discloses wherein the dielectric layer 130 comprises SiN (see paragraph [0066] of Song).
In re claim 23, as applied to claim 22 above, Song in combination with Li discloses wherein the dopant comprises Si, F, or B (see paragraph [0070] of Li).
In re claim 24, as applied to claim 23 above, Song in combination with Li discloses wherein an implantation energy of the implantation process ranges from about 0.2 keV to about 5 keV (see paragraph [0073] of Song).
In re claim 25, as applied to claim 24 above, Song discloses wherein an implantation temperature of the implantation process is less than 600 °C (see paragraph [0070]) but is silent to wherein the implantation process ranges from about -60 degrees Celsius to about 450 degrees Celsius.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art to optimize the implantation temperature ranges to be from about -60 degrees Celsius to about 450 degrees Celsius during routine experimentation since where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See in re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
In re claim 26, as applied to claim 25 above, Song in combination with Li discloses wherein an implantation tilt angle of the implantation process ranges from about 0 degrees to about 15 degrees (see paragraph [0070] of Li).
In re claim 27, as applied to claim 26 above, Song in combination with Li discloses wherein a dopant concentration in the dielectric layer increases in a direction away from the first semiconductor material (see paragraph [0070] of Li).
Claim(s) 11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (U.S. Pub. 2023/0378264) in view of Li et al. (U.S. Pub. 2017/0358663), as applied to claim 8 above, and further in view of Lin et al. (U.S. Pub. 2014/0273366).
In re claim 11, as applied to claim 8 above, Song and Li are silent to wherein the annealing process comprises flash lamp annealing (FLA), laser spike annealing (LSA), or rapid thermal annealing (RTA).
However, Lin discloses in a same field of endeavor, a method of forming a semiconductor device, including, inter-alia, wherein the annealing process comprises rapid thermal anneal (RTA) (see paragraph [0027]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Lin into the method of Song in order to enable to use the rapid thermal annealing (RTA) technique for annealing the dielectric layer in Song to be performed in order to minimize dopant diffusion, precise temperature control, and reduce contamination.
In re claim 13, as applied to claim 11 above, Song and Li are silent to wherein the annealing process comprises RTA, an annealing temperature ranges from about 600 degrees Celsius to about 1000 degrees Celsius, and a dwell time of the annealing process ranges from about 1 S to about 20 S.
However, Lin discloses in a same field of endeavor, a method for forming a semiconductor device including, inter-alia, wherein the annealing process comprises RTA, an annealing temperature ranges from about 300 degrees Celsius to about 1000 degrees Celsius, and a dwell time of the annealing process ranges from about 0.01 second to about 10 seconds (see paragraph [0027]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Lin into the method of Song in order to enable wherein the annealing process comprises RTA, an annealing temperature ranges from about 600 degrees Celsius to about 1000 degrees Celsius, and a dwell time of the annealing process ranges from about 1 S to about 20 S in Song to be performed in order to minimize dopant diffusion, precise temperature control, and reduce contamination. Furthermore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art to optimize the implantation temperature ranges to be from about 600 degrees Celsius to about 1000 degrees Celsius and a dwell time for the annealing process to be in a ranges from about 1 S to about 20 S during routine experimentation since where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See in re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (U.S. Pub. 2023/0378264) in view of Li et al. (U.S. Pub. 2017/0358663), and Lin et al. (U.S. Pub. 2014/0273366), as applied to claim 11 above, and further in view of Cheng et al. (U.S. Pub. 2020/0152589).
In re claim 12, as applied to claim 11 above, Song, Li, and Lin are silent to wherein the annealing process comprises FLA or LSA, an annealing temperature ranges from about 1050 degrees Celsius to about 1200 degrees Celsius, and a dwell time of the annealing process ranges from about 0.1 ms to about 40 ms.
However, Cheng discloses in a same field of endeavor, a method for forming a semiconductor device, including, inter-alia, wherein the annealing process comprises FLA, an annealing temperature ranges from about 325 degrees Celsius to about 500 degrees Celsius (see paragraph [0028]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Cheng into the method of Song in order to enable wherein the annealing process comprises FLA or LSA, an annealing temperature ranges from about 1050 degrees Celsius to about 1200 degrees Celsius, and a dwell time of the annealing process ranges from about 0.1 ms to about 40 ms in Song to be performed in order to suppress dopant diffusion and provide high energy efficiency. Furthermore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art to optimize the annealing temperature ranges to be from about 1050 degrees Celsius to about 1200 degrees Celsius and a dwell time for the annealing process to be in a ranges from about 0.1 ms to about 40 ms during routine experimentation since where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See in re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
Allowable Subject Matter
Claims 16-20 are allowed over prior art of record.
Reasons For Allowance
The following is an examiner’s statement of reasons for allowance:
It is determined that the prior art of record neither anticipates nor renders obvious the claimed subject matter of independent claim 16 as a whole taken alone or in combination, in particular, prior art of record does not teach “recessing the second plurality of semiconductor layers to form cavities; forming dielectric spacers in the cavities; wherein the dielectric layer comprises a sidewall portion in contact with the gate spacer, the first plurality of semiconductor layers, and the dielectric spacers”.
Claims 17-20 also allowed as being directly or indirectly dependent of the allowed independent base claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang et al. (U.S. Pub. 2022/0093743) discloses a method, comprising forming a sacrificial gate stack 134 over a portion of a fin structure 112 (see paragraph [0037] and fig. 5); removing an exposed portion of the fin structure to expose a portion of a substrate 101 and a surface of a semiconductor layer 108 of the fin structure 112 (see paragraph [0037] and fig. 5); and depositing a first semiconductor material 146 on the exposed portion of the substrate 101 (see paragraph [0044] and figs. 9A, 9B).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
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