DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without express traverse of Invention I, claims 1-15, and Species B (Fig. 2D) in the reply filed on 20 May 2026 is acknowledged. Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. The election requirement is deemed proper and made final.
Response to Amendment
The Office acknowledges receipt on 20 May 2026 of Applicant’s amendments in which claim 7 is amended, withdrawn claims 16-20 are cancelled, and claims 21-25 are newly added.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thei et al. (US20190363079A1) in view of Yang et al. (US20170171978A1).
Regarding claim 1, Thei teaches in Figs. 3 and 4 semiconductor structure, comprising:
a first interconnect structure (108a) disposed over a first semiconductor substrate (106a) {[0017]}; and
a first bonding structure (118a, 120a, 132a) disposed on and electrically coupled to the first interconnect structure (108a), [and] conductive features ([112, 114, 116, 162], [118, 120]) of the first interconnect structure (108a) and the first bonding structure (118a, 120a, 132a) {[0023]}.
Thei does not teach thermal sensors embedded in the first interconnect structure and sensing temperature variations in the semiconductor structure, and the thermal sensors being electrically isolated from conductive features of the first interconnect structure and the first bonding structure.
In an analogous art, Yang teaches in Fig. 4B and paragraphs [0017, 0025] thermal sensors (TS1, TS2) embedded in an interconnect structure (300A, 500, 300B) and sensing temperature variations in a semiconductor structure (10B), the thermal sensors (TS1, TS2) being electrically isolated from conductive features (CND1, 301, 302, 520) of the interconnect structure (300A, 500, 300B) and a first bonding structure (300B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure based on the teachings of Yang – to include thermal sensors embedded in the first interconnect structure and sensing temperature variations in the semiconductor structure, and the thermal sensors being electrically isolated from conductive features of the first interconnect structure and the first bonding structure – so a temperature measurement of an area surrounding the temperature sensors due to one or more particular heat sources may be acquired without being significantly influenced by a thermal conductivity path through an electrical conductivity path of the one or more particular heat sources. Moreover, all the claimed elements (e.g., thermal sensors, interconnect structure, conductive features, bonding structure) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 8, Thei as modified by Yang teaches the semiconductor structure of claim 1, but Thei does not teach further comprising:
first devices disposed on a first region, a first set of the thermal sensors being arranged to sense the temperature variations of the first region; and
second devices disposed on a second region, a second set of the thermal sensors being arranged to sense the temperature variations of the second region, the first devices consuming a higher amount of power than the second devices, wherein a distribution density of the first set of the thermal sensors is greater than that of the second set of the thermal sensors.
Yang teaches in Fig. 4B first devices (e.g., CP4 and nearby electrical connections) disposed on a first region, a first set (TS2) of the thermal sensors (TS1, TS2) being arranged to sense the temperature variations of the first region; and second devices (e.g., CP1, CP2, CP3 and nearby electrical connections) disposed on a second region, a second set (TS1) of the thermal sensors (TS1, TS2) being arranged to sense the temperature variations of the second region, the first devices consuming a higher amount of power than the second devices, wherein a distribution density of the first set of the thermal sensors is greater than that of the second set of the thermal sensors {see annotated copy of Yang’s Fig. 4B below}. The motivation for this modification is identified with respect to the rejection of claim 1.
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Regarding claim 9, Thei as modified by Yang teaches the semiconductor structure of claim 1, and Thei further teaches wherein the first bonding structure (118a, 120a, 132a) comprises a first bonding dielectric layer (132a) and a first bonding feature (118a) covered by the first bonding dielectric layer (132a) and electrically coupled to the conductive features ([112, 114, 116, 162]) of the first interconnect structure (108a), and bonding surfaces (134) of the first bonding dielectric layer (132a) and the first bonding feature (118a) are substantially leveled {[0048]}.
“The Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
Claim(s) 2 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thei in view of Yang as applied to claim 1 above, and further in view of Horng et al. (US20160290873A1).
Regarding claim 2, Thei as modified by Yang teaches the semiconductor structure of claim 1, and Thei further teaches further comprising:
first transistors (302) disposed over the first semiconductor substrate (106a) and underneath the first interconnect structure (108a), the first transistors (3020) being electrically coupled to the conductive features ([112, 114, 116, 162]) of the first interconnect structure (108a) {Fig. 3; [0028]}; and
the thermal sensors (TS1 in the modified structure of claim 1), embedded in the first interconnect structure (modified 108a) over the first transistors (302), and electrically isolated from the conductive features of the first interconnect structure (modified 108a) {this subject matter is repetitive to that recited in claim 1 and fully accounted for in claim 1}.
Thei does not teach second transistors included in the thermal sensors.
In an analogous art, Horng teaches in Fig. 2B and paragraph [0047] second transistors (256, 266) included in a thermal sensor (250). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang based on the teachings of Horng – such that second transistors are included in each of Yang’s thermal sensors – to generate a proportional to absolute temperature (PTAT) current based on a temperature. Horng [0049].
Regarding claim 5, Thei as modified by Yang teaches the semiconductor structure of claim 1, but Thei does not teach wherein the thermal sensors comprise thermal sensing components at different levels of the first interconnect structure, and the thermal sensing components comprise a resistance value with a thermal dependency.
Yang teaches in Fig. 4B that thermal sensors (TS1, TS2) comprise thermal sensing components (TS1, TS2) at different levels of an interconnect structure (300A, 500, 300B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang based on the further teachings of Yang – to include thermal sensing components at different levels of the first interconnect structure – so as to acquire temperature measurements at different elevations of the of the interconnect structure. Moreover, all the claimed elements (e.g., thermal sensors, thermal sensing components, levels of the first interconnect structure) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Thei as modified by Yang does not teach the thermal sensing components comprise a resistance value with a thermal dependency.
Horng teaches in Fig. 2B and paragraph [0047] a thermal sensing component (254) comprises a resistance value (R) with a thermal dependency. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang based on the teachings of Horng – such that Yang’s thermal sensing components comprise a resistance value with a thermal dependency – to generate a proportional to absolute temperature (PTAT) current based on a temperature. Horng [0049]. Moreover, all the claimed elements (e.g., thermal sensing components, resistance value, thermal dependency) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Horng) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 3 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thei in view of Yang and Horng as applied to claim 2 (for claim 3) and claim 5 (for claim 6) above, and further in view of Ghani et al. (US20250159953A1).
Regarding claim 3, Thei as modified by Yang and Horng teaches the semiconductor structure of claim 2, but Thei does not teach wherein the second transistors comprise a two-dimensional (2D) material channel layer.
In an analogous art, Ghani teaches in paragraph [0045] a transistor (110) comprises a (2D) material channel layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang and Horng based on the teachings of Ghani – such that Yang’s thermal sensing components, as modified by Horng, comprise a two-dimensional (2D) material channel layer – because all the claimed elements (e.g., transistors, two-dimensional (2D) material channel layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ghani) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 6, Thei as modified by Yang and Horng teaches the semiconductor structure of claim 5, but Thei does not teach wherein the thermal sensing components comprise a 2D material layer.
Ghani teaches in paragraph [0045] a thermal sensing component (channel material of 110) comprises a (2D) material channel layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang and Horng based on the teachings of Ghani – such that Yang’s thermal sensing component, as modified by Horng, comprise a two-dimensional (2D) material layer – because all the claimed elements (e.g., transistors, two-dimensional (2D) material layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ghani) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thei in view of Yang as applied to claim 1 above, and further in view of Horng and Lin et al. (US10581426B1).
Regarding claim 4, Thei as modified by Yang teaches the semiconductor structure of claim 1, and Thei further teaches further comprising:
transistors (302) disposed over the first semiconductor substrate (106a) and underneath the first interconnect structure (108a), the transistors (302) comprising a first transistor (302) electrically coupled to the conductive features ([112, 114, 116, 162]) of the first interconnect structure (108a) {[0028]}.
Thei does not teach a second transistor electrically coupled to the thermal sensors.
Horng teaches in Fig. 2B and paragraph [0047] a second transistor (256/266) electrically coupled to a thermal sensor (250). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang based on the teachings of Horng – such that a second transistor is electrically coupled to Yang’s thermal sensor – to generate a proportional to absolute temperature (PTAT) current based on a temperature. Horng [0049]. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Thei as modified by Yang and Horng does not teach the second transistor is electrically coupled to multiple thermal sensors.
In an analogous art, Lin teaches in Fig. 19 a transistor (150) is electrically coupled to multiple thermal sensors (1900). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang and Horng based on the teachings of Lin – such that the second transistor is electrically coupled to multiple thermal sensors – to minimize the impact of process variation in the construction of the individual temperature diodes. Lin col. 13, lines 32-35. Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thei in view of Yang, Horng, and Ghani as applied to claim 6 above, and further in view of Kamgaing (US20150255372A1).
Regarding claim 7, Thei as modified by Yang and Horng teaches the semiconductor structure of claim 6, but Thei does not teach wherein one of the thermal sensing components is a two-terminal device which comprises two terminals disposed at opposing sides of the 2D material layer.
In an analogous art, Kamgaing teaches in Fig. 6 and paragraph [0059] a two-terminal device (642, 644) which comprises two terminals (644) disposed at opposing sides of a 2D material layer (642). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang, Horng, and Ghani based on the teachings of Kamgaing – such that one of Yang’s thermal sensing components, as modified by Horng and Ghani, is a two-terminal device which comprises two terminals disposed at opposing sides of the 2D material layer – because all the claimed elements (e.g., thermal sensing component, two-terminal device, 2D material layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Kamgaing) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thei in view of Yang as applied to claim 1 above, and further in view of Kao et al. (DE102019123600B4) using Kao et al. (US20230369173A1) as the English translation.
Regarding claim 10, Thei as modified by Yang teaches the semiconductor structure of claim 1, but Thei does not teach further comprising:
a second interconnect structure disposed over a second semiconductor substrate;
a through substrate via penetrating through the second semiconductor substrate and electrically coupled to the second interconnect structure; and
a second bonding structure disposed below the second semiconductor substrate and electrically coupled to the second interconnect structure through the through substrate via, the second bonding structure being bonded to the first bonding structure, and a bonding interface of the first and second bonding structure being substantially leveled.
In an analogous art, Kao teaches in Fig. 8C a second interconnect structure (116) disposed over a second semiconductor substrate (108) {[0024]}; a through substrate via (104) penetrating through the second semiconductor substrate (108) and electrically coupled to the second interconnect structure (116) {[0024]}; and a second bonding structure (upper 112b) disposed below the second semiconductor substrate (108) and electrically coupled to the second interconnect structure (116) through the through substrate via (104) {[0058]}, the second bonding structure (upper 112b) being bonded to a first bonding structure (lower 112b), and a bonding interface (828) of the first and second bonding structure (112b) being substantially leveled. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang based on the teachings of Kao, to achieve the above-identified features, for the purpose of providing electrical connectivity between the first and second interconnect structures. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Kao) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
“The Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thei in view of Yang and Monferrer et al. (US20080236175A1).
Regarding claim 11, Thei teaches in Figs. 3 and 4 a semiconductor structure, comprising:
a hot spot region (region over 150 and/or 302b) over a semiconductor substrate (106b) {[0017, 0028]};
an interconnect structure (108b) over the semiconductor substrate (106b) {[0017]}.
Thei does not teach thermal sensors embedded in different levels of the interconnect structure.
Yang teaches in Fig. 4B thermal sensors (TS1, TS2; TS1; or multiple combinations of TS1 and TS2) embedded in different levels of an interconnect structure (110, 200, 300A, 500, 300B, 400) {[0016]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure based on the further teachings of Yang – to include thermal sensors embedded in different levels of the interconnect structure – so as to acquire temperature measurements at different elevations of the of the interconnect structure. Moreover, all the claimed elements (e.g., thermal sensors, levels of the first interconnect structure) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Thei as modified by Yang does not teach the thermal sensors comprising first sensors monitoring a temperature change of the hot spot region and second sensors monitoring a temperature change of a region outside the hot spot region, and the first sensors being arranged in a denser manner than the second sensors.
In an analogous art, Monferrer teaches in Fig. 3 and paragraphs [0016, 0021] thermal sensors (214) comprising first sensors (214b) monitoring a temperature change of a hot spot region and second sensors (214c) monitoring a temperature change of a region outside the hot spot region, and the first sensors (214b) being arranged in a denser manner than the second sensors (214c) {see annotated copy of Monferrer’s Fig. 3}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang based on the teachings of Monferrer – to include thermal sensors comprising first sensors monitoring a temperature change of the hot spot region and second sensors monitoring a temperature change of a region outside the hot spot region, and the first sensors being arranged in a denser manner than the second sensors – so the temperature sensors … may be positioned … at regions likely to become hot spots and such hot spots may not be regularly distributed. Monferrer [0021]. Moreover, all the claimed elements (e.g., first sensors, hot spot region, second sensors, region outside the hot spot region) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Monferrer) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
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Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thei in view of Yang and Monferrer as applied to claim 11 above, and further in view of Horng, Ghani, and Or-Bach et al. (US20210407991A1).
Regarding claim 12, Thei as modified by Yang and Monferrer teaches the semiconductor structure of claim 11, and Thei further teaches a transistor (302) disposed over the semiconductor substrate (106b) and underneath the interconnect structure (108b).
Thei further teaches in paragraph [0028] the transistor (302) may be a MOSFET, which is pertinent to the discussion below.
Thei does not teach each of the thermal sensors comprises a control transistor comprising a channel layer.
Horng teaches in Fig. 2B and paragraph [0047] a thermal sensor (250) comprises a control transistor (256/266) comprising a channel layer (implicit). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang and Monferrer based on the teachings of Horng – such that each of Yang’s thermal sensors comprises a control transistor comprising a channel layer – to generate a proportional to absolute temperature (PTAT) current based on a temperature. Horng [0049].
Thei does not teach expressly that the channel layer of the control transistor comprises a particular material.
Ghani teaches in paragraph [0045] a transistor (110) comprises a (2D) material channel layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang, Monferrer, and Horng based on the teachings of Ghani – such that each of Horng’s control transistors comprise a two-dimensional (2D) material channel layer made of graphene – because all the claimed elements (e.g., transistors, two-dimensional (2D) material channel layer of graphene) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ghani) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Thei does not teach the channel layer of the control transistor comprises a material different from a channel material of the transistor (disclosed by Thei, as discussed above).
As mentioned above, Thei teaches the transistor (302) disposed over the semiconductor substrate (106a) and underneath the first interconnect structure (108a) may be a MOSFET.
In an analogous art, Or-Bach teaches in paragraph [0105] a MOSFET having a channel layer of Si or Ge. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang, Monferrer, Horng, and Ghani based on the teachings of Or-Bach – such that Thei’s transistor comprises a channel material of Si/Ge – because all the claimed elements (e.g., transistor, channel of Si/Ge) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Or-Bach) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
A consequence of this modification is that the control transistor comprises a material different from a channel material of the transistor.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thei in view of Yang, Monferrer, Horng, Ghani, and Or-Bach and as applied to claim 12 above, and further in view of Ogawa et al. (US20240426887A1).
Regarding claim 13, as interpreted in view of the indefiniteness rejection, Thei as modified by Yang, Monferrer, Horng, Ghani, and Or-Bach teaches the semiconductor structure of claim 12, and Thei further teaches a conductive material (e.g., Cu) of conductive features (112/114/116/122/124/128/130) of the interconnect structure (108b) {Fig. 2; [0022]}.
Thei does not teach the material of the channel layer of the control transistor has a higher temperature coefficient of resistance than the conductive material (identified immediately above).
In an analogous art, Ogawa teaches in Fig. 15 and paragraphs [0192, 0186, 0164, 0057] a transistor with a 2D graphene material channel layer has a temperature coefficient of resistance of several hundred %/K. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang, Monferrer, Horng, Ghani, and Or-Bach based on the teachings of Ogawa – such that Horng’s control transistor has a channel layer material with a relatively high temperature coefficient of resistance – to better determine gradations of temperature. Moreover, all the claimed elements (e.g., material of a channel layer, control transistor, temperature coefficient of resistance) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ogawa) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Copper has a temperature coefficient of resistance of approximately 0.393 %/K; and copper is the material of Thei’s conductive features (112/114/116/122/124/128/130) of the interconnect structure (108a), as discussed above.
Accordingly, a consequence of Ogawa’s modification is that the modified channel layer of the control transistor has a higher temperature coefficient of resistance than Thei’s conductive material.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thei in view of Yang and Monferrer and as applied to claim 11 above, and further in view of Horng and Ghani.
Regarding claim 14, Thei as modified by Yang and Monferrer teaches the semiconductor structure of claim 11, but Thei does not teach wherein each of the thermal sensors comprises:
at least one control transistor covered by a dielectric layer of the interconnect structure; and
sensing components connected to the at least one control transistor and distributed at the different levels of the interconnect structure, the sensing components being disposed in proximity to the hot spot region.
Yang teaches in Fig. 4B thermal sensors (multiple thermal sensors, each individual sensor being a combination of TS1 and TS2) that each comprises sensing components (TS1, TS2) distributed at different levels of an interconnect structure (110, 200, 300A, 500, 300B, 400) {[0016]}, the sensing components (TS1, TS2) being disposed in proximity to a hot spot region (region of CP1-CP4). The motivation for this modification is identified with respect to base claim 11.
Thei does not teach each of the thermal sensors comprises at least one control transistor.
Horng teaches in Fig. 2B and paragraph [0047] a thermal sensor (Fig. 2B) comprises a control transistor (256/266). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang and Monferrer based on the teachings of Horng – such that each of Yang’s thermal sensors or sensing components comprises a control transistor – to generate a proportional to absolute temperature (PTAT) current based on a temperature. Horng [0049].
Thei does not teach each of the thermal sensors is covered by a dielectric layer of the interconnect structure.
Yang teaches in in Fig. 4B thermal sensors (multiple combinations of TS1 and TS2) covered by a dielectric layer (112) of the interconnect structure (110, 200, 300A, 500, 300B, 400) {the orientation of Yang’s Fig. 4B may be rotated to match the claimed orientation}. The motivation for this modification is identified with respect to base claim 11. A consequence of this modification is that a control transistor of each thermal sensor is covered by a dielectric layer of the interconnect structure.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thei in view of Yang, Monferrer, Horng, and Ghani and as applied to claim 14 above, and further in view of Ogawa.
Regarding claim 15, Thei as modified by Yang and Monferrer teaches the semiconductor structure of claim 14, and Thei further teaches a conductive material (e.g., Cu) of conductive features (112/114/116/122/124/128/130) of the interconnect structure (108b) {Fig. 2; [0022]}.
Thei does not teach the sensing components comprise a particular material.
Ghani teaches in paragraph [0045] a transistor (110) comprises a (2D) material channel layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang, Monferrer, and Horng based on the teachings of Ghani – such that each of Horng’s control transistors comprise a two-dimensional (2D) material channel layer made of graphene – because all the claimed elements (e.g., transistors, two-dimensional (2D) material channel layer of graphene) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ghani) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Thei does not teach the material of the sensing components has a higher temperature coefficient of resistance than the conductive material (identified above).
In an analogous art, Ogawa teaches in Fig. 15 and paragraphs [0192, 0186, 0164, 0057] a transistor with a 2D graphene material channel layer has a temperature coefficient of resistance of several hundred %/K. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Thei’s semiconductor structure as modified by Yang, Monferrer, Horng, and Ghani based on the teachings of Ogawa – such that Yang’s sensing component (as modified by Horng and Ghani) has a channel layer material with a relatively high temperature coefficient of resistance – to better determine gradations of temperature. Moreover, all the claimed elements (e.g., material of a channel layer, control transistor, temperature coefficient of resistance) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ogawa) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Copper has a temperature coefficient of resistance of approximately 0.393 %/K; and copper is the material of Thei’s conductive features (112/114/116/122/124/128/130) of the interconnect structure (108a), as discussed above.
Accordingly, a consequence of Ogawa’s modification is that the modified channel layer of the control transistor has a higher temperature coefficient of resistance than Thei’s conductive material.
Claim(s) 21, 24, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (DE102019123600B4) using Kao et al. (US20230369173A1) as the English translation in view of Yang and Horng.
Regarding claim 21, Kao teaches in Fig. 8C a semiconductor structure, comprising:
a first tier (804) comprising {[0055]}:
first semiconductor devices (812) {[0055]};
a first interconnect structure (810) electrically coupled to the first semiconductor devices (812) {[0055]};
a first bonding structure (structure of 112b, 830 within 804) disposed over and electrically coupled to the first interconnect structure (810) {[0058]}; and
a second tier (802) comprising a second bonding structure (structure of 112b, 806 within 802) bonded to the first bonding structure (structure of 112b within 804) of the first tier (804) {[0053, 0054, 0058]}.
Kao does not teach thermal sensing components embedded in the first interconnect structure and sensing a hot spot generated by the first semiconductor devices.
Yang teaches in Fig. 4B and paragraphs [0027, 0029] temperature sensors (TS1, TS2) embedded in an interconnect structure (300A, 500, 300B) and sensing temperature variations (e.g., a hot spot) generated by semiconductor devices (CP1-CP4). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kao’s semiconductor structure based on the teachings of Yang – to include temperature sensors embedded in the first interconnect structure and sensing a hot spot generated by the first semiconductor devices – so a temperature of an area surrounding the temperature sensors due to one or more particular heat sources may be acquired without being significantly influenced by a thermal conductivity path through an electrical conductivity path of the one or more particular heat sources. Moreover, all the claimed elements (e.g., temperature sensors, interconnect structure, semiconductor devices) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Kao as modified by Yang does not teach control devices embedded in the first interconnect structure, the control devices being coupled to the thermal sensing components and generating an electrical characteristic varying with temperature.
However, as discussed immediately above, Yang teaches temperature sensors embedded in an interconnect structure.
Horng teaches in Fig. 2B and paragraph [0047] a temperature sensor includes a thermal sensing component (R) coupled to a control device (e.g., 256, 266, 262, 272). Horng further teaches in the cited material the control device (e.g., 256, 266, 262, 272) generates an electrical characteristic (e.g., PTAT current) varying with temperature. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kao’s semiconductor structure as modified by Yang based on the teachings of Horng – such that each of Yang’s temperature sensors, which are embedded in an interconnect structure, includes a control device coupled to a thermal sensing component and generating an electrical characteristic varying with temperature – to measure a temperature … during operation to help control the temperature. Horng [0002].
Regarding claim 24, Kao as modified by Yang and Horng teaches the semiconductor structure of claim 21, and Kao further teaches wherein:
the first bonding structure (structure of 112b, 830 within 804) comprises a first dielectric layer (830) and a first conductive feature (112b within 804), a bonding surface of the first dielectric layer (830) is substantially coplanar with a bonding surface of the first conductive feature (112b within 804) {[0053-0055, 0058]},
the second bonding structure (structure of 112b, 806 within 802) comprises a second dielectric layer (806) bonded to the first dielectric layer (830) and a second conductive feature (112b within 802) bonded to the first conductive feature (112b within 804), and a bonding surface of the second dielectric layer (806) is substantially coplanar with a bonding surface of the second conductive feature (112b within 802) {[0053-0055, 0058]}.
Regarding claim 25, Kao as modified by Yang and Horng teaches the semiconductor structure of claim 21, and Kao further teaches wherein the second tier (802) further comprises {[0053]}:
a second interconnect structure (116) {[0053]};
a semiconductor substrate (108) disposed between the second bonding structure (structure of 112b, 806 within 802) and the second interconnect structure (116) {[0053]};
[a] second semiconductor device (106) disposed on the semiconductor substrate (108) {[0053]}.
Kao does not teach a plurality of second semiconductor devices on the semiconductor substrate.
However, the instant application does not identify a new and unexpected result being produced by having a plurality of second semiconductor devices on the semiconductor substrate, rather than a single second semiconductor device. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Kao’s semiconductor structure to include a plurality of second semiconductor devices on the semiconductor substrate because mere duplication of parts has no patentable significance unless a new and unexpected result is produced. MPEP §2144.04 (VI)(B).
Kao does not teach thermal sensors embedded in the second interconnect structure and monitoring a temperature change of a hot spot generated by the second semiconductor devices.
Yang teaches in Fig. 4B and paragraphs [0027, 0029] thermal sensors (TS1, TS2) embedded in an interconnect structure (300A, 500, 300B) and sensing temperature variations (e.g., a hot spot) generated by semiconductor devices (CP1-CP4). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kao’s semiconductor structure based on the teachings of Yang – to include thermal sensors embedded in the second interconnect structure and monitoring a temperature change of a hot spot generated by the second semiconductor devices – so a temperature of an area surrounding the temperature sensors due to one or more particular heat sources may be acquired without being significantly influenced by a thermal conductivity path through an electrical conductivity path of the one or more particular heat sources. Moreover, all the claimed elements (e.g., temperature sensors, interconnect structure, semiconductor devices) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Yang and Horng and as applied to claim 21 above, and further in view of Bernstein et al. (US20090121260A1) and Ghani.
Regarding claim 22, Kao as modified by Yang and Horng teaches the semiconductor structure of claim 21, but Kao does not teach wherein: one of the control devices comprises a gate electrode, source/drain features, a channel layer disposed below the gate electrode and laterally disposed between the source/drain features, and the channel layer comprises a 2D material.
Horng teaches in Fig. 2B a control device (e.g., 256, 266, 262, 272) comprises a gate electrode and source/drain features {e.g., each of FETs 256 and 266 includes a gate electrode and source/drain features}. The motivation for this modification is identified with respect to base claim 21.
Kao as modified by Horng does not teach that each control device has a channel layer disposed below the gate electrode and laterally disposed between the source/drain features.
In an analogous art, Bernstein teaches in Fig. 1A and paragraph [0020] a control device (130) has a channel layer (140) disposed below a gate electrode (145) and laterally disposed between source/drain features (135). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kao’s semiconductor structure as modified by Yang and Horng based on the teachings of Bernstein – such that each of Horng’s control devices has a channel layer disposed below the gate electrode and laterally disposed between the source/drain features – because all the claimed elements (e.g., control device, channel layer, gate electrode, source/drain features) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Bernstein) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Kao as modified by Horng does not teach the channel layer comprises a 2D material.
Ghani teaches in paragraph [0045] a transistor (110) comprises a (2D) material channel layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kao’s semiconductor structure as modified by Yang, Horng, and Bernstein based on the teachings of Ghani – such that each of Bernstein’s channel layers comprises a 2D material – because all the claimed elements (e.g., channel layer, two-dimensional (2D) material) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ghani) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Yang, Meyer et al. (US20060071700A1), Bernstein and Ghani.
Regarding claim 23, Kao teaches a semiconductor structure, comprising:
a first tier (804) comprising:
first semiconductor devices (812);
a first interconnect structure (810) electrically coupled to the first semiconductor devices (812);
a first bonding structure (structure of 112b within 804) disposed over and electrically coupled to the first interconnect structure (810); and
a second tier (802) comprising a second bonding structure (structure of 112b within 802) bonded to the first bonding structure (structure of 112b within 804) of the first tier (804).
Kao does not teach thermal sensing components embedded in the first interconnect structure and sensing a hot spot generated by the first semiconductor devices.
Yang teaches in Fig. 4B and paragraphs [0027, 0029] temperature sensors (TS1, TS2) embedded in an interconnect structure (300A, 500, 300B) and sensing temperature variations (e.g., a hot spot) generated by semiconductor devices (CP1-CP4). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kao’s semiconductor structure based on the teachings of Yang – to include temperature sensors embedded in the first interconnect structure and sensing a hot spot generated by the first semiconductor devices – so a temperature of an area surrounding the temperature sensors due to one or more particular heat sources may be acquired without being significantly influenced by a thermal conductivity path through an electrical conductivity path of the one or more particular heat sources. Moreover, all the claimed elements (e.g., temperature sensors, interconnect structure, semiconductor devices) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Kao as modified by Yang does not teach control devices embedded in the first interconnect structure, the control devices being coupled to the thermal sensing components and generating an electrical characteristic varying with temperature.
In an analogous art, Meyer teaches in Figs. 1 and 3 and paragraph [0008] a temperature sensor comprises a MOS transistor (metal oxide semiconductor transistor) and a bipolar transistor, the MOS transistor being integrated into the semiconductor body in such a way that the subthreshold current intensity of the MOS transistor rises or falls when there is a change in the temperature to be measured. The MOS transistor is connected up to the bipolar transistor in such a way that the subthreshold current of the MOS transistor is amplified by the bipolar transistor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kao’s semiconductor structure as modified by Yang based on the teachings of Meyer – such that each of Yang’s temperature sensors includes a control device that is coupled to a thermal sensing component as taught by Meyer for generating an electrical characteristic varying with temperature – for measuring the temperature. Meyer [0008]. Moreover, all the claimed elements (e.g., control devices, thermal sensing components) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Meyer) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. A consequence of this modification, in view of Yang’s modification, is that each of the control devices is embedded in Kao’s first interconnect structure.
Kao as modified by Yang and Meyer does not teach expressly that one of the thermal sensing components comprises a channel layer and terminals coupled to the channel layer.
However, Meyer teaches that each thermal sensing component is an FET.
Bernstein teaches in Fig. 1A and paragraph [0020] an FET (130) has a channel layer (140) disposed below a gate electrode (145) and laterally disposed between source/drain features (135). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kao’s semiconductor structure as modified by Yang and Meyer based on the teachings of Bernstein – such that each of Meyer’s thermal sensing devices comprises a channel layer and terminals coupled to the channel layer – because all the claimed elements (e.g., channel layer, terminals) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Bernstein) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Kao as modified by Yang, Meyer, and Bernstein does not teach the channel layer comprises a 2D material.
Ghani teaches in paragraph [0045] a transistor (110) comprises a (2D) material channel layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kao’s semiconductor structure as modified by Yang, Meyer, and Bernstein based on the teachings of Ghani – such that each of Bernstein’s channel layers comprises a 2D material – because all the claimed elements (e.g., channel layer, two-dimensional (2D) material) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ghani) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Burd et al. (US20240321668A1) teaches a method for die pair partitioning can include providing a first circuit die having a first metal stack. The method can additionally include positioning a second circuit die having a second metal stack in a manner that places a temperature sensor in a transistor layer of the second circuit die in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die. The method can also include connecting the first metal stack of the first circuit die to the second metal stack of the second circuit die.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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