DETAILED ACTION
This correspondence is in response to the communications received 05/19/2026. Claims 14-20 have been withdrawn. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-13 in the reply filed on 05/19/2026 is acknowledged.
Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected inventive group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/19/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/04/2024 has been considered by the examiner and made of record in the application file.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, an electronic device (100A), comprising:
a substrate (110);
a conductive connector (150), disposed on the substrate (see Fig. 1D);
a conductive bonding material (199), disposed on the conductive connector (see Fig. 1D); and
a spacer layer (180), laterally covering the conductive connector (see Fig. 1D).
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Regarding claim 11, a semiconductor structure (300E), comprising:
a first electronic device, comprising:
a first substrate (111);
a first conductive connector (151), disposed on the first substrate (see Fig. 3E);
a first spacer layer (381), laterally covering the first conductive connector (see Fig. 3E);
a second electronic device, comprising:
a second substrate (112);
a second conductive connector (152), disposed on the second substrate (see Fig. 3E);
a second spacer layer (382), laterally covering the second conductive connector (see Fig. 3E); and
a conductive bonding layer (190), disposed between the first conductive connector and the second conductive connector (see Fig. 3E).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 9,524,945 B2, published 12/20/2016) in view of Tsao et al. (US 11,127,704 B2, published 09/21/2021).
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Regarding claim 1, Figs. 3A-3G of Hwang disclose an electronic device (“FIGS. 3A-3G are cross-sectional views depicting another exemplary embodiment of a portion of a semiconductor device at stages in a Cu pillar bump process, while explanation of the same or similar portions to the description in FIGS. 1A to 1F will be omitted”, col. 6, lines 50-54), comprising:
a substrate (“semiconductor substrate 10”, col. 6, line 60);
a conductive connector (“Cu pillar 20”, col. 7, line 18, Cu is known in the art as conductive, and as seen in Fig. 3G, 20 connects 10 to “substrate 100”, col. 7, line 38), disposed on the substrate;
a conductive bonding material (“joint solder layer 102”, col. 7, lines 40-41, solder is known in the art as conductive, however Hwang does not disclose that 102 is a bonding material, therefore a secondary reference will be used to teach this limitation below), disposed on the conductive connector; and
a spacer layer (“L-shaped sidewall spacers 22a”, col. 7, line 21), laterally covering the conductive connector (as seen in Fig. 3G, 22a laterally covers 20).
Hwang fails to disclose “a conductive bonding material”.
However, in a similar field of endeavor, Figs. 1-14 of Tsao teach a conductive bonding material (“The bump structures 55 of the first and second semiconductor devices 10, 10′ are brought into contact with each other and energy is applied to cause the solder layers 35, 35′ to soften and flow into each other, and then fuse to form an intermetallic bond at the solder joint 90”, col. 8, lines 50-54).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a conductive bonding material” as taught by Tsao in the system of Hwang for the purpose of providing a bond between adjacent semiconductor devices.
Regarding claim 2, Figs. 3A-3G of Hwang in combination with Figs. 1-14 of Tsao disclose the electronic device of claim 1, Figs. 3A-3G of Hwang further disclose wherein a melting point of the conductive bonding material is lower than a melting point of the conductive connector, and the melting point of the conductive bonding material is lower than a melting point of the spacer layer (“An exemplary coupling process includes a flux application, chip placement, reflowing of melting solder joints, and cleaning of flux residue”, col. 5, lines 60-63, thus as the coupling process requires melting 102, 102 must necessarily have a lower melting point than 20 and 22a in order for the structure to remain intact during reflow).
Regarding claim 3, Figs. Figs. 3A-3G of Hwang in combination with Figs. 1-14 of Tsao disclose the electronic device of claim 1, Figs. Figs. 3A-3G of Hwang further disclose wherein a material of the spacer layer is an inorganic material (“protection layer 22 is a non-metal material layer, for example a dielectric material layer”, col. 5, lines 1 and 2 where “a protection layer 22 is formed to cover the resulted structure. After performing a CMP process, an L-shaped sidewall spacer 22a is created”, col. 7, lines 19-21, one having ordinary skill in the art would understand that dielectric materials are non-organic).
Regarding claim 4, Figs. 3A-3G of Hwang in combination with Figs. 1-14 of Tsao disclose the electronic device of claim 1, Figs. 3A-3G of Hwang further disclose wherein a maximum dimension of the spacer layer is along a thickness direction of the electronic device (as seen in Fig. 3G, the maximum dimension of 22a is along a thickness direction of the electronic device).
Regarding claim 5, Figs. 3A-3G of Hwang in combination with Figs. 1-14 of Tsao disclose the electronic device of claim 1, Figs. 3A-3G of Hwang further discloses wherein the spacer layer further covers a portion of the conductive bonding material (as seen in Fig. 3G, 22a covers a portion of 102).
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Regarding claim 11, Figs. 1-14 of Tsao disclose a semiconductor structure (see title), comprising:
a first electronic device (“first semiconductor device 10”, col. 8, lines 39-40), comprising:
a first substrate (“substrate 15”, col. 8, lines 38);
a first conductive connector (“pillar 25”, col. 3, line 13, where “pillar 25 [is] formed mainly of a metal”, pillar 25 formed mainly of a metal”, col. 3, line 13, metals are known in the art as conductive, and as seen in Fig. 14, 25 connects 15 to 15’), disposed on the first substrate (as seen in Fig. 14, 25 is disposed on 15);
a second electronic device (“second semiconductor device 10′”, col. 8, lines 40-41), comprising:
a second substrate (“substrate 15’”, col. 8, lines 38);
a second conductive connector (pillar “25’” denoted in Fig. 14 is the corresponding version of 25 for 10’), disposed on the second substrate (depending on the relative perspective of Fig. 14, 25’ is on 15’);
a conductive bonding layer (“solder joint 90”, col. 8, line 54, where “The bump structures 55 of the first and second semiconductor devices 10, 10′ are brought into contact with each other and energy is applied to cause the solder layers 35, 35′ to soften and flow into each other, and then fuse to form an intermetallic bond at the solder joint 90”, col. 8, lines 50-54), disposed between the first conductive connector and the second conductive connector (as seen in Fig. 14, 90 is disposed between 25 and 25’).
Tsao fails to disclose “a first spacer layer, laterally covering the first conductive connector; and
a second spacer layer, laterally covering the second conductive connector”.
However, in a similar field of endeavor, Figs. 3A-3G of Hwang disclose a first spacer layer (“L-shaped sidewall spacers 22a”, col. 7, line 21), laterally covering the first conductive connector (as seen in Fig. 3G, 22a laterally covers “Cu pillar 20”, col. 7, line 18, where 20 of Hwang is equivalent to 25 and 25’ of Tsao); and
a second spacer layer, laterally covering the second conductive connector (as Tsao discloses two symmetric structures, one having ordinary skill in the art could add 22a of Hwang to both 25 and 25’ of Hwang).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first spacer layer, laterally covering the first conductive connector; and
a second spacer layer, laterally covering the second conductive connector” as taught by Hwang in the system of Tsao for the purpose of increasing “adhesion between the Cu pillar sidewall and a subsequently formed underfill material” (Hwang, col. 6, lines 2-3).
Regarding claim 12, Figs. 1-14 of Tsao in combination with Figs. 3A-3G of Hwang disclose the semiconductor structure of claim 11, Figs. 1-14 of Tsao further disclose further comprising:
a filling material (“an underfill material 95”), disposed between the first substrate and the second substrate (as seen in Fig. 14, 95 is disposed between 15 and 15’), wherein the first spacer layer and the second spacer layer are laterally encapsulated by the filling material (after combination of Tsao and Hwang, 22a of Hwang will be directly in contact with 25 and 25’ of Tsao, therefore 22a will be laterally encapsulated by 95).
Regarding claim 13, Figs. 1-14 of Tsao in combination with Figs. 3A-3G of Hwang disclose the electronic device of claim 11, Figs. 3A-3G of Hwang further discloses wherein a portion of the conductive bonding layer (“joint solder layer 102”, col. 7, lines 40-41, equivalent to 90 of Tsao) is covered by the first spacer layer and/or the second spacer layer (as seen in Fig. 3G, 22a covers a portion of 102).
Claims 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 9,524,945 B2, published 12/20/2016) in view of Tsao et al. (US 11,127,704 B2, published 09/21/2021) in view of Solo De Zaldivar (US 20060278982 A1, published 12/14/2006).
Regarding claim 6, Figs. 3A-3G of Hwang in combination with Figs. 1-14 of Tsao disclose the electronic device of claim 1.
Hwang in combination with Tsao fails to disclose “wherein the substrate comprises:
a patterned conductive layer, wherein the spacer layer is in contact with a portion of a top surface of the patterned conductive layer”.
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However, in a similar field of endeavor, Figs. 1a-1e and 2 of Solo de Zaldivar teach wherein the substrate comprises:
a patterned conductive layer (“diffusion stop barrier 4'”, [0034], metals are known in the art as conductive, further, “Those portions of the metal layer 4 which are exposed between the side walls are then removed … The remaining portions of the metal layer 4 form a diffusion stop barrier 4'”, [0035], thus 4 is patterned into 4’), wherein the spacer layer (“insulation layer 7 “, [0034], equivalent to 22a of Hwang) is in contact with a portion of a top surface of the patterned conductive layer (as seen in Fig. 2, 7 is in contact with a portion of a top surface of 4’).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the substrate comprises:
a patterned conductive layer, wherein the spacer layer is in contact with a portion of a top surface of the patterned conductive layer” as taught by Solo de Zaldivar in the system of Hwang in combination with Tsao for the purpose of preventing atomic migration from the conductive connector to the substrate.
Regarding claim 7, Figs. 3A-3G of Hwang in combination with Figs. 1-14 of Tsao and Figs. 1a-1e and 2 of Solo de Zaldivar disclose the electronic device of claim 6, Figs. 1a-1e and 2 of Solo de Zaldivar further disclose wherein the spacer layer is not in contact with a side surface of the patterned conductive layer (as seen in Fig. 2, 7 is not in contact with a side surface of 4’).
Regarding claim 8, Figs. 3A-3G of Hwang in combination with Figs. 1-14 of Tsao and Figs. 1a-1e and 2 of Solo de Zaldivar disclose the electronic device of claim 6, Figs. 1a-1e and 2 of Solo de Zaldivar further disclose wherein a side surface of the spacer layer is substantially aligned with a side surface of the patterned conductive layer (as seen in Fig. 2, a side surface of 7 is substantially aligned with a side surface of 4’) .
Regarding claim 9, Figs. 3A-3G of Hwang in combination with Figs. 1-14 of Tsao disclose the electronic device of claim 1.
Hwang in combination with Tsao fails to disclose “further comprising:
a filling material, disposed on the substrate, wherein the spacer layer is disposed between the conductive connector and the filling material”.
However, in a similar field of endeavor, Figs. 1a-1e and 2 of Solo de Zaldivar teach further comprising:
a filling material (as seen in 2, the material denoted “FM” is a filling material that fills the region between “substrate 2”, [0031], and “opposite substrate 9”, [0036]), disposed on the substrate (as seen in Fig. 2, FM is disposed on 2), wherein the spacer layer is disposed between the conductive connector and the filling material (as seen in Fig. 2, 7 is between “bumps 6a, 6b”, [0033], equivalent to 20 of Hwang, and FM).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “further comprising:
a filling material, disposed on the substrate, wherein the spacer layer is disposed between the conductive connector and the filling material” as taught by Solo de Zaldivar in the system of Hwang in combination with Tsao for the purpose of protecting the device from mechanical or moisture related damage.
Regarding claim 10, Figs. 3A-3G of Hwang in combination with Figs. 1-14 of Tsao and Figs. 1a-1e and 2 of Solo de Zaldivar disclose the electronic device of claim 9, Figs. 1a-1e and 2 of Solo de Zaldivar further disclose wherein the substrate comprises:
a patterned conductive layer (“diffusion stop barrier 4'”, [0034], metals are known in the art as conductive, further, “Those portions of the metal layer 4 which are exposed between the side walls are then removed … The remaining portions of the metal layer 4 form a diffusion stop barrier 4'”, [0035], thus 4 is patterned into 4’), wherein the spacer layer (“insulation layer 7 “, [0034], equivalent to 22a of Hwang) is in contact with a portion of a top surface of the patterned conductive layer (as seen in Fig. 2, 7 is in contact with a portion of a top surface of 4’), and the filling material is in contact with a side surface of the patterned conductive layer (as seen in Fig. 2, FM is in contact with a side surface of 4’).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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