Prosecution Insights
Last updated: July 17, 2026
Application No. 18/403,754

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

Non-Final OA §102
Filed
Jan 04, 2024
Priority
Dec 14, 2023 — provisional 63/609,872
Examiner
LINDSEY, COLE LEON
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
113 granted / 127 resolved
+21.0% vs TC avg
Moderate +13% lift
Without
With
+12.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
16 currently pending
Career history
158
Total Applications
across all art units

Statute-Specific Performance

§103
84.3%
+44.3% vs TC avg
§102
8.6%
-31.4% vs TC avg
§112
6.7%
-33.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 127 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 9 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Arana et al. (US20080237841A1, hereinafter Arana). Regarding claim 9, Arana teaches a package structure, comprising: an interconnection structure (Fig. 1 substrate 110); a plurality of first semiconductor dies disposed on a center region of the interconnection structure and electrically connected to the interconnection structure (Fig. 1 die 120 in central region); a plurality of second semiconductor dies disposed on peripheral regions of the interconnection structure and electrically connected to the interconnection structure (Fig. 1 peripheral dies 130/140); a first heat dissipation component disposed on and covering backside surfaces of the plurality of first semiconductor dies (Fig. 1 thermal interface material 121 disposed in central region); a second heat dissipation component disposed on and covering backside surfaces of the plurality of second semiconductor dies (Fig. 1 thermal interface materials 131/141 disposed over dies in peripheral region), wherein the first heat dissipation component and the second heat dissipation component comprises different materials (Par. 18 teaches that “[s]everal types of thermal interface material exist in the industry, and thermal interface materials 121, 131, and 141 may be chosen from” the options listed in paragraph 18); and a lid structure disposed on and in contact with the first heat dissipation component and the second heat dissipation component, and laterally surrounding the first heat dissipation component, the second heat dissipation component, the plurality of first semiconductor dies, the plurality of second semiconductor dies and the interconnection structure (Fig. 1 lid 153). Allowable Subject Matter Claims 1-8 and 16-20 allowed. Claims 10-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 1 and its dependent claims. The closest prior art (US20080237841A1, US20210118770A1, US20190067157A1) teaches a package structure, comprising: a circuit substrate (Arana fig. 1 substrate 110); a semiconductor package disposed on and electrically connected to the circuit substrate, wherein the semiconductor package comprises a center region and peripheral regions (Arana fig. 1 die 120 in central region with peripheral dies 130/140); a thermal interface material structure disposed on the center region and on the peripheral regions of the semiconductor package (Arana fig. 1 thermal interface material 121 disposed in central region with thermal interface materials 131/141 disposed over peripheral regions); a plating layer disposed on the thermal interface material structure (Lin fig. 20 dummy connectors 118); a first intermetallic compound formed in between the thermal interface material structure and the plating layer over the center region of the semiconductor package (Lin par. 64 teaches that “[d]uring reflow, the nickel coating of the heat spreader 208 mingles with the material of the TIM 212 and dummy connectors 118 to form an intermetallic compound (IMC) 126 at the interface of the heat spreader 208 and TIM 212”); and a lid structure disposed on the circuit substrate and covering the semiconductor package (Arana fig. 1 lid 153). However, the closest prior art does not teach in combination with the other claimed elements a second intermetallic compound formed in between the thermal interface material structure and the plating layer over the peripheral regions of the semiconductor package, wherein the second intermetallic compound is different from the first intermetallic compound Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims. Examiner notes that while there are embodiments within the prior art, see Lin par. 64, that teach how an IMC may be formed during a reflow process during production of a heat spreading device, examiner's search of the prior art did not find an embodiment nor any motivation to combine embodiments such that a second intermetallic compound formed in between the thermal interface material structure and the plating layer over the peripheral regions of the semiconductor package and the second intermetallic compound is different from the first intermetallic compound in addition with the other limitations of the independent claim. Regarding claim 10 and its dependent claims. The closest prior art (US20080237841A1, US20210118770A1, US20190067157A1) teaches the package structure according to claim 9, wherein the first heat dissipation component comprises a first thermal interface material, and a first plating layer disposed on the first thermal interface material (Lin par. 64 teaches that “[d]uring reflow, the nickel coating of the heat spreader 208 mingles with the material of the TIM 212 and dummy connectors 118 to form an intermetallic compound (IMC) 126 at the interface of the heat spreader 208 and TIM 212”). However, the closest prior art does not teach in combination with the other claimed elements the second heat dissipation component comprises a second thermal interface material, and a second plating layer disposed on the second thermal interface material, wherein the second thermal interface material and the first thermal interface material include different materials or the second plating layer and the first plating layer include different materials. Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims. Examiner notes that while there are embodiments within the prior art, see Lin par. 64, that teach how an IMC may be formed during a reflow process during production of a heat spreading device, examiner's search of the prior art did not find an embodiment nor any motivation to combine embodiments such that the second heat dissipation component comprises a second thermal interface material and a second plating layer disposed on the second thermal interface material wherein the second thermal interface material and the first thermal interface material include different materials or the second plating layer and the first plating layer include different materials in addition with the other limitations of the independent claim. Regarding claim 16 and its dependent claims. The closest prior art (US20080237841A1, US20210118770A1, US20190067157A1) teaches a method of fabricating a package structure, comprising: disposing a semiconductor package on a circuit substrate (Arana fig. 1 substrate 110), wherein the semiconductor package comprises a center region and peripheral regions (Arana fig. 1 die 120 in central region with peripheral dies 130/140); forming a thermal interface material structure on the center region and on the peripheral regions of the semiconductor package (Arana fig. 1 thermal interface material 121 disposed in central region with thermal interface materials 131/141 disposed over peripheral regions); disposing a plating layer on the thermal interface material structure and a lid structure on the circuit substrate, wherein the lid structure is contacting the plating layer and covering the semiconductor package (Lin fig. 20 dummy connectors 118); and performing a heating process for forming a first intermetallic compound in between the thermal interface material structure and the plating layer over the center region of the semiconductor package (Lin par. 64 teaches that “[d]uring reflow, the nickel coating of the heat spreader 208 mingles with the material of the TIM 212 and dummy connectors 118 to form an intermetallic compound (IMC) 126 at the interface of the heat spreader 208 and TIM 212”). However, the closest prior art does not teach in combination with the other claimed elements forming a second intermetallic compound in between the thermal interface material structure and the plating layer over the peripheral regions of the semiconductor package, wherein the second intermetallic compound is different from the first intermetallic compound. Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims. Examiner notes that while there are embodiments within the prior art, see Lin par. 64, that teach how an IMC may be formed during a reflow process during production of a heat spreading device, examiner's search of the prior art did not find an embodiment nor any motivation to combine embodiments such that a second intermetallic compound is formed in between the thermal interface material structure and the plating layer over the peripheral regions of the semiconductor package and wherein the second intermetallic compound is different from the first intermetallic compound in addition with the other limitations of the independent claim. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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Prosecution Timeline

Jan 04, 2024
Application Filed
Apr 23, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+12.9%)
2y 10m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 127 resolved cases by this examiner. Grant probability derived from career allowance rate.

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