Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-16, in the reply filed on 05/08/2026 is acknowledged. Claims 17-20 withdrawn. Claims 1-16 are examined below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the second bumps being distributed in the second region of the first substrate ". There is insufficient antecedent basis for this limitation in the claim because “the second region” is not introduced prior. Applicant is required to amend the claim to clarify the antecedent basis, for example by reciting “a second region of the first substrate”.
Claims 2-10 are rejected under 35 U.S.C. 112(b) for being dependent on claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (CN 114759003 A).
Re: Independent Claim 1, Lin discloses a package structure, comprising:
a first substrate comprising first bumps with first lateral dimension and second bumps with second lateral dimension (Lin teaches, in Fig. 4A, semiconductor package SM3 with interposed 100’ comprising first bumps 118A in region AR1 with first lateral dimension and second bumps 118B in BR1A region with second lateral dimension), the first bumps being distributed in a first region of the first substrate (Fig. 4A, first bumps 118A are in the central region AR1), and the second bumps being distributed in the second region of the first substrate (Fig. 4A, second bumps 118B are in the side region BR1A), wherein the first lateral dimension is greater than the second lateral dimension (Fig. 4A, lateral dimension of 118A is greater than the lateral dimension of 118B), and a first bump height of the first bumps is smaller than a second bump height of the second bumps (Fig. 4A, height HT of 118A is smaller than height H1 of 118B); and
a second substrate comprising conductive terminals electrically connected to the first bumps and the second bumps (As stated by Lin, in the exemplary embodiment, the semiconductor package SM3 shown in FIG. 4 A and FIG. 4 B may be mounted or bonded to the circuit substrate 300 in a manner similar to that shown in FIGS. 3 A to 3 C. Thus, circuit substrate 300 with contact pads 310 and the bump structure 118 (118A/118B) is physically attached to the connection bump, so as to be electrically connected to the circuit substrate 300 electrically connected to 118A and 118B of Fig. 4A).
Re: Claim 6, Lin discloses all the limitations of claim 1 on which this claim depends.
Lin further teaches
wherein the first substrate further comprises third bumps with third lateral dimension, and the third bumps are distributed in a third region of the first substrate (Lin teaches, in Fig. 4A, third bumps 118B with lateral dimension in region BR1B).
Re: Claim 7, Lin discloses all the limitations of claim 6 on which this claim depends.
Lin further teaches
wherein the third lateral dimension is less than the first lateral dimension and greater than the second lateral dimension (Lin Fig. 4B, lateral dimension of third bumps 118B-1 in region BR1B-4 portion of third region BR1B is less than the lateral dimension of 118A in first region AR1, and greater than the lateral dimension of second bumps 118B-2 in region BR1A-2).
Re: Claim 8, Lin discloses all the limitations of claim 6 on which this claim depends.
Lin further teaches
wherein the third lateral dimension is less than the first lateral dimension and substantially equals to the second lateral dimension (Lin Fig. 4B, lateral dimension of third bumps 118B-1 in region BR1B-4 portion of third region BR1B is less than the lateral dimension of 118A in first region AR1, and equal to the lateral dimension of second bumps 118B-1 in region BR1A-1).
Re: Claim 9, Lin discloses all the limitations of claim 6 on which this claim depends.
Lin further teaches
wherein a third bump height of the third bumps is smaller than the first bump height or substantially equals to the first bump height (Li states “the height difference between the first bump structure 118A and the second bump structure 118B is still kept in the ratio range of 1: 1.1 to 1: 1.25”. Thus, with the heigh ratio of 1:1.1, height of third bumps 118B-1 in region BR1B is only about 10% greater than the height HT of the first bumps 118A. Thus, Lin reasonably teaches third bumps 118B-1 in region BR1B is substantially equal to the height HT of the first bumps 118A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (CN 114759003 A) in view of Qi (US 6774497 B1).
Re: Claim 2, Lin discloses all the limitations of claim 1 on which this claim depends.
Lin is silent regarding
further comprising: a non-conductive film laterally encapsulating the first bumps and the second bumps, wherein a thickness of the non-conductive film is smaller than the first bumps height and the second bump height.
However, Qi teaches further comprising: a non-conductive film laterally encapsulating the first bumps and the second bumps, wherein a thickness of the non-conductive film is smaller than the first bumps height and the second bump height (Qi teaches, in Fig. 2B and related descriptions, underfill material 230 (230 comprises a material such as an epoxy, a thermoplastic material, a thermoset material, polyimide, polyurethane, a polymeric material) applied to a bumped flip chip 210 and around side regions 222 of connective bumps 220. Qi further teaches that the thickness of underfill material 230 is less than the height of connective bumps 220, for example about 20% to 60% of the bump height. Accordingly, Qi’s underfill material 230 corresponds to the claimed non-conductive film).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin to include Qi’s thin underfill material 230 around Lin’s first and second bump structure 118A/118B, with the underfill thickness selected to be smaller than the height of the shortest first bump structures 118A and therefore also smaller than the height of the taller second bump structures 118B, in order to provide stress relief and moisture protection.
Re: Claim 3, Lin and Qi disclose all the limitations of claim 2 on which this claim depends.
Qi further teaches
further comprising: a passivation layer laterally encapsulating the conductive terminals, wherein the passivation layer is in contact with the non-conductive film (Qi teaches, in Fig. 2B and related descriptions, electrical substrate 240 having pads 242 corresponding to the connective bumps 220, and solder mask 250 covering the substrate surface with holes/open portions above pads 242. Qi further teaches that connective bumps 220 are places through holes or windows in the solder mask 250 corresponding to pads 242, such that solder mask 250 laterally surrounds the pads/terminals. Qi further teaches that underfill material 230 wets/bonds to solder mask 250 and that underfill material 230 and solder mask 250 combine to form a stress-relief layer and moisture-penetration barrier. Therefore, Qi teaches the passivation layer being in contact with the non-conductive film.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include Qi’s solder mask/passivation layer around Li’s conductive contact pads 310 and to have the thin underfill/non-conductive film contact the solder-mask/passivation layer, in order to constrain solder flow, protect pads and traces, improve adhesive bonding, provide moisture protection, and improve solder joint reliability.
Claim(s) 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (CN 114759003 A) in view of Lee (US 20100155920 A1).
Re: Claim 4, Lin discloses all the limitations of claim 1 on which this claim depends.
Lin is silent regarding
wherein the second bumps protrude into the conductive terminals.
However, Lee teaches
wherein the second bumps protrude into the conductive terminals (Lee teaches, in Figs. 1 and 4, and ¶ [0038], first/lower semiconductor package 200 having first circuit board 104, substrate pad 106, via hole 140, and conductive member 118 disposed in via hole 140. Lee further teaches second/upper semiconductor package 400 having stud bump 124, wherein stud bump 124 is inserted into/protrudes into conductive member 118 to electrically connect the first and second semiconductor packages. Lee also teaches, in its claim 2, that the stud bump includes a protruding portion extending into the conductive member, and that the protruding portion may include a convex portion to increase connection strength).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin so that Lin’s second bump structures 118B protrude into conductive terminals on circuit substrate 300, as taught by Lee, in order to improve electric/mechanical connection reliability and increase joint strength.
Re: Claim 5, Lin discloses all the limitations of claim 1 on which this claim depends.
Lin is silent regarding
wherein the first bumps and the second bumps protrude into the conductive terminals. However, Lee teaches
wherein the first bumps and the second bumps protrude into the conductive terminals (Lee teaches, in Figs. 1 and 4, and ¶ [0038], first/lower semiconductor package 200 having first circuit board 104, substrate pad 106, via hole 140, and conductive member 118 disposed in via hole 140. Lee further teaches second/upper semiconductor package 400 having stud bump 124, wherein stud bump 124 is inserted into/protrudes into conductive member 118 to electrically connect the first and second semiconductor packages. Lee also teaches, in its claim 2, that the stud bump includes a protruding portion extending into the conductive member, and that the protruding portion may include a convex portion to increase connection strength).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin so that Lin’s first bump structures 118A and second bump structures 118B protrude into corresponding conductive terminals, such as conductive connection bumps or solder conductive members on contact pads 310, as taught by Lee, in order to improve electric/mechanical connection reliability and increase joint strength.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (CN 114759003 A) in view of Shen (US 20130069231 A1).
Re: Claim 10, Lin discloses all the limitations of claim 1 on which this claim depends.
Lin is silent regarding
wherein each of the conductive terminals comprises a bump portion and a solder portion covering the bump portion, and the solder portion of each of the conductive terminals is in contact with to one of the first bumps or one of the second bumps.
However, Shen teaches
wherein each of the conductive terminals comprises a bump portion and a solder portion covering the bump portion (Shen teaches, in Fig. 2E, solder cap bump 240 including conductive pillar 217 and a solder cap 220’ formed over the top surface of conductive pillar 217. Shen’s solder cap bump 240 corresponds to the claimed conductive terminal, conductive pillar 217 corresponds to the claimed bump portion, and solder cap 220’ corresponds to the claimed solder portion covering the bump portion), and the solder portion of each of the conductive terminals is in contact with to one of the first bumps or one of the second bumps (Shen further teaches, in Fig. 3A, that in forming a flip-chip package, bonding structure 200’ is flipped over and bonded with carrier substrate 310, and solder cap 220’ is disposed into pad opening 316 t electrically connect with bond pad 312. Shen teaches that controlling the solder cap volume improves solder cap height uniformity and provides better interconnection between solder caps 220’ and bond pads 312, thereby enhancing semiconductor package reliability).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s conductive terminals connection bumps on contact pads 310 of circuit substrate 300 to have Shen’s solder-cap bump structure, i.e., conductive pillar 217 with solder cap 220’ thereon, so that solder cap 220’ contacts one of Lin’s first bump structures 118A or second bump structures 118B during bonding in order to improve bump-height uniformity, provide better interconnection, and enhance package reliability, as taught by Shen.
Claim(s) 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (CN 114759003 A) in view of Qi (US 6774497 B1) further in view of Shen (US 20130069231 A1).
Re: Independent Claim 11, Lin discloses a package structure, comprising:
a substrate comprising first bumps, second bumps (Lin teaches, in Fig. 4A, semiconductor package SM3 with interposed 100’ comprising first bumps 118A in region AR1 and second bumps 118B in BR1A region, wherein the first bumps are wider than the second bumps (Lin Fig. 4B, first bumps 118A are wider than the second bumps 118B), and the second bumps are higher than the first bumps (Lin Fig. 4B, the second bumps 118B are higher than first bumps 118A).
Lin is silent regarding
a dielectric layer laterally encapsulating the first and second bumps; a semiconductor die bonded to the substrate; the semiconductor die comprising a passivation layer bonded to the dielectric layer.
However, Qi teaches
a dielectric layer laterally encapsulating the first and second bumps; a semiconductor die bonded to the substrate; the semiconductor die comprising a passivation layer bonded to the dielectric layer (Qi teaches, in Fig. 2B, underfill material 230 applied on bumped flip chip 210 and around side regions 222 of connective bumps 220. Accordingly, Qi’s underfill material 230 corresponds to the claimed dielectric layer because it is an insulating underfill/polymer material surrounding the bump interconnects. Qi also teaches solder mask 250 on electric substrate 240, with opening above pads 242. Accordingly, solder mask 250 corresponds to a passivation layer. Qi further teaches that underfill material 230 wets and bonds to solder mask 250, and that the underfill material 230 and solder mask 250 cooperate to form a stress-relief layer and moisture barrier.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s to use Qi’s underfill/dielectric material 230 around Lin’s first and second bump structures 118a/118B, and to have the underfill/dielectric material bond to a passivation/solder-mask layer of the opposing component, in order to improve adhesion, stress relief, moisture protection, and solder-joint reliability).
Lin is further silent regarding
the semiconductor die comprising first conductive terminals embedded in the passivation layer, and second conductive terminals embedded in the passivation layer, wherein the first conductive terminals are bonded to the first bumps, the second conductive terminals are bonded to the second bumps, and the first conductive terminals are wider than the second conductive terminals.
However, Shen teaches
the semiconductor die comprising first conductive terminals embedded in the passivation layer, and second conductive terminals embedded in the passivation layer, wherein the first conductive terminals are bonded to the first bumps, the second conductive terminals are bonded to the second bumps, and the first conductive terminals are wider than the second conductive terminals (Shen teaches, Fig. 3A and related descriptions, a semiconductor device 200 including a semiconductor substrate 210, pads 212, and passivation layer 214 coated on the top surface of semiconductor substrate 210. Shen teaches that passivation layer 214 is patterned to expose portions of pad 212, and conductive pillars 217 are formed and electrically connected with pads 212. Shen further teaches that solder ball 220 is disposed on the top surface of conductive pillar 217 and reflowed to form solder cap 220’ having cap profile over the top surface of conductive pillar 217, thereby forming solder cap bump 240. Accordingly, Shen’s semiconductor device 200 corresponds to the claimed semiconductor die, passivation layer 214 corresponds to the claimed passivation layer, and conductor pillars 217/solder cap bumps 240 correspond to conductive terminals embedded in the passivation layer.
Shen further teaches, in ¶ [0031], a flip-chip package in which bonding structure 200’ is flipped over and bonded with carrier substrate 310, and solder cap 220’ is disposed into pad opening 316 to electrically connect with bond pad 312. Shen teaches that controlling solder cap volume improves solder-cap height uniformity, provides better interconnection between solder caps 220’ and bond pads 312, and further enhance the reliability of the semiconductor package).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use Shen’s semiconductor die-side passivation/terminal structure with the package structure of Lin and Qi, such that the semiconductor die includes passivation layer 214 and first/second conductive terminals, such as conductive pillars 217 and solder caps 220’, embedded in or laterally surrounded by passivation layer 214 and bonded to Lin’s first and second bump structures 118A/118B in order to provide a better interconnection between the bump-to-terminal bonding and enhance the reliability of the semiconductor package.
It further would have been obvious for the first conductive terminals to be wider than the second conductive terminals. Lin already teaches wider first bump structures 118A with wider metallization patterns 116b and narrower second bump structures 118B with narrower metallization patterns 116b. Therefore, a person of ordinary skill in the art would have been motivated to size the mating die-side conductive terminals correspondingly, so that wider first conductive terminals bond to wider first bump structures 118A and narrower second conductive terminals bond to narrower second bump structures 118B, in order to improve alignment tolerance for larger bumps and reducing bridging risk for smaller/narrower bumps.
Re: Claim 12, Lin, Qi and Shen disclose all the limitations of claim 11 on which this claim depends.
Lin further teaches
wherein a height difference between the first bumps and the second bumps ranges from about 1 micrometer to about 2 micrometers (Lin teaches that the first bump structures 118A have a height of HT, and the second bump structures 118B having a height H1, where the height HT and height H1 are measured from the bottom of the metal pillars MP1/MP2 to the tip of the solders SDL1/SDL2. Lin teaches that the height HT of the first bump structures 118A is smaller than the height H1 of second bump structures 118B, and that the height difference is maintained after welding. Lin also teaches that metal pillars MP1 of the first bump structures 118A may have a height range of 70 μm to 95 μm, and metal pillars MP2 of the second bump structures 118B may have a height of 85 μm to 110 μm, with MP2 being greater in height than MP1. Because Lin’s disclosed pillar height ranges overlap, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to understand that Lin encompasses selecting MP1 and MP2 heights such that MP2 is greater than MP1 by about 1 μm to about 2 μm, for example selecting MP1 near the upper end of its disclosed range and MP2 slightly greater within its disclosed range).
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (CN 114759003 A) in view of Qi (US 6774497 B1) further in view of Shen (US 20130069231 A1) and further in view of Lee (US 20100155920 A1).
Re: Claim 13, Lin, Qi and Shen disclose all the limitations of claim 11 on which this claim depends.
Lin, Qi and Shen are silent regarding
wherein the second bumps protrude into the second conductive terminals.
However, Lee teaches
wherein the second bumps protrude into the second conductive terminals (Lee teaches, in Figs. 1 and 4, and ¶ [0038], first/lower semiconductor package 200 having first circuit board 104, substrate pad 106, via hole 140, and conductive member 118 disposed in via hole 140. Lee further teaches second/upper semiconductor package 400 having stud bump 124, wherein stud bump 124 is inserted into/protrudes into conductive member 118 to electrically connect the first and second semiconductor packages. Lee also teaches that the stud bump includes a protruding portion extending into the conductive member, and that the protruding portion may include a convex portion to increase connection strength).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin so that Lin’s second bump structures 118B protrude into corresponding second conductive terminals on circuit substrate 300, as taught by Lee, in order to improve electric/mechanical connection reliability and increase joint strength.
Claim(s) 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (CN 114759003 A) in view of Qi (US 6774497 B1) further in view of Shen (US 20130069231 A1) and further in view of Yu (US 20140167254 A1).
Re: Claim 14, Lin, Qi and Shen disclose all the limitations of claim 11 on which this claim depends.
Lin, Qi and Shen are silent regarding
wherein the substrate further comprises dummy bumps laterally encapsulated by the dielectric layer.
However, Yu teaches
wherein the substrate further comprises dummy bumps laterally encapsulated by the dielectric layer (Yu teaches, in Figs. 1 and 4 and ¶ [0010], semiconductor chip 100 with dummy bumps 28D that do not serve electrical connection between chip 100 and another substrate. Yu further teaches that dummy bumps 28D are positioned on passivation layer 18. Yu also teaches, ¶ [0030], applying underfill material to fill the space between the first substrate 10 and the second substrate 220A to prevent cracks in solder joint regions. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of Lin to further include Yu’s dummy bumps 28D on the substrate, and to have the dielectric/underfill material laterally encapsulate those dummy bumps along with the first and second bump structures, in order to improve mechanical support, standoff uniformity, underfill formation quality, and package reliability).
Re: Claim 15, Lin, Qi and Shen disclose all the limitations of claim 14 on which this claim depends.
Lin, Qi and Shen are silent regarding
wherein the first bumps are higher than the dummy bumps.
However, Yu teaches
wherein the first bumps are higher than the dummy bumps (Yu teaches, in Fig. 4 and ¶ [0016], first bump structures 28A have height HA which is higher than the dummy bumps 28D height HD. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of Lin, Qi and Shen to include Yu’s dummy bump arrangement in which the active/first bumps are higher than the dummy bumps, in order to control bump-height coplanarity, improve standoff uniform, improve quality of dispensing underfill in the package structure which can reduce assembly risk raised by bump bridging and cold joint issues).
Re: Claim 16, Lin, Qi and Shen disclose all the limitations of claim 14 on which this claim depends.
Lin, Qi and Shen are silent regarding
wherein the first bumps and the dummy bumps are substantially identical in height.
However, Yu teaches
wherein the first bumps and the dummy bumps are substantially identical in height (Yu teaches, in ¶ [0016], first bump structures 28A have height HA which may be equal to the dummy bumps 28D height HD. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of Lin, Qi and Shen to include Yu’s dummy bump arrangement in which the active/first bumps are higher than the dummy bumps, in order to control bump-height coplanarity, improve standoff uniform, improve quality of dispensing underfill in the package structure which can reduce assembly risk raised by bump bridging and cold joint issues).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 11:30am-7:30pm.
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/BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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