DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species H, represented by figure 8, in the reply filed on May 4, 2026 is acknowledged.
Claim 30 is withdrawn from consideration as it is not directed to Species H as it is not disclosed in the disclosure. Claim 30 requires…
wherein the first MRAM unit includes a lower electrode, a magnetic tunneling junction (MTJ) layer, a capping layer, and an upper electrode disposed in sequence over the first memory transistor, and the lower electrode of the first MRAM unit is electrically connected to a drain structure of the first memory transistor.
After searching the specification, Examiner was unable to find a capping layer disclosed in the specification. Figure 1 is the closest to the claim. Figure 1 shows a via 511, a top electrode 504, a memory element 503 (which is the MJT), a bottom electrode comprising two layers 502 and 501, and a bottom via 511. There is no “capping layer” disclosed to be above the MJT layer 503 and the top electrode 504. Therefore, new claim 30 contains new matter, and because it is new matter is not directed to Species H. Hence, claim 30 is withdrawn from consideration.
Information Disclosure Statement
As of May 21, 2026, no information disclosure statement has been made of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-29, and 31-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lim (US 2024/0072092 A1) (“Lim”), in view of Choi et al. (US 2023/0039809 A1) (“Choi”).
Regarding claim 21, Lim teaches at least in figure 8:
a first wafer (100),
including a first substrate (110) and a first interconnect structure (120);
an image sensor (elements in 110; hereinafter “A”), disposed in the first substrate (110) and configured to receive an optical signal from a backside of the first substrate (160 is the backside of 110, and A is an image sensor so it is configured as claimed);
a second wafer (200),
including a second substrate (210) and a second interconnect structure (220),
wherein the second wafer (210) is disposed at a front side of the first substrate (110);
a pixel transistor array (PX comprising SX, SF, SW1, SW2), disposed in the second substrate (210);
a third wafer (300),
including a third substrate (310) and a third interconnect structure (320),
wherein the third wafer (300) is disposed at the front side of the first substrate (110) and electrically connecting to the first wafer through the second wafer (vias 410/420 provide the claimed electrical connection);
a logic device (250/350), disposed in the third substrate (310) and configured to process an electrical signal generated by the optical signal from the image sensor (250/350 can so be configured);
a first memory device (¶ 0065 capaciotors in 220), disposed in the second wafer (200).
Lim does not teach:
The first memory device including a first MRAM unit; and
a second memory device, disposed in the third wafer and including a second MRAM unit.
This is because Lim teaches one of the second wafer includes capacitor memory, and the third wafer include the logic devices.
Choi teaches at least in figure 4:
That the second wafer 300 can include logic and memory, and the third wafer 400 can include logic and memory.
One of ordinary skill in the art would be motivated to use the wafers of Choi in the device of Lim because Choi teaches that by adding the logic and memory to the second wafer and third wafer one can simplify the manufacturing process and reduce the total size of the device. ¶ 0067. Further, by adding both the logic and memory cells to the second and third wafer one can create a temporary image storage to improve the processing of the image and reduce the Zello effect. Id.
Choi also teaches that DRAM, or capacitor memory, is functionally equivalent to MRAM, ¶ 0066, and can be used as the memory in the second and third wafer. MPEP 2144.06-07.
Based upon the above Choi teaches at least in figure 4:
The first memory device (memory in 300) including a first MRAM unit (figure 4); and
a second memory device (memory in 400), disposed in the third wafer (400) and including a second MRAM unit (¶ 0066).
Regarding claim 22, the combination of Choi and Lim teach:
wherein the first memory device (Choi ¶ 0065; Lim memory in 300) comprises (detailed below):
a first memory transistor (Choi any one of the transistors in 200), disposed in the second substrate (Choi 200; Lim 300); and
the first MRAM unit (Lim ¶ 0067), disposed in the second interconnect structure (Choi’s DRAM as in the second interconnect structure).
Regarding claim 23, the combination of Choi and Lim teach:
wherein the first MRAM unit electrically connects to the first memory transistor through the second interconnect structure (This would have been obvious as Choi teaches there are several TSVs (P2b’ P1b) that electrically connect the memory transistors though the second interconnect structure shown in 200; Further, it would have been obvious to one of ordinary skill in the art to do this as it would allow them to store the pixel data to memory.).
Regarding claim 24, the combination of Choi and Lim teach:
wherein the first MRAM unit vertically overlaps the first memory transistor (the MRAM of Lim would overlap the transistor in the same manner that the DRAM of Choi overlaps the transistors of Choi).
Regarding claim 25, the combination of Choi and Lim teach:
Claim 25 is rejected for the same reasons as claim 24 above.
Regarding claim 26, the combination of Choi and Lim teach:
wherein the second memory device comprises: a second memory transistor, disposed in the third substrate; and the second MRAM unit, disposed in the third interconnect structure (this is a duplication of Choi 200, and as shown in Lim 400 would be a duplication of Lim 300. Therefore, this limitation is taught be the combination of Choi and Lim.).
Regarding claim 27, the combination of Choi and Lim teach:
The claim would be obvious for the same reasons given in claim 23 above.
Regarding claim 28, the combination of Choi and Lim teach:
wherein the first memory device vertically aligned with the second memory device (it would have been obvious that to simplify the manufacturing process as taught by Lim, ¶ 0066, one would want the orientations of the memory devices in each of the second and third wafer to align. This would make interconnection between the second and third wafer easier.).
Regarding claim 29, the combination of Choi and Lim teach:
wherein the first memory device electrically connects to the pixel transistor array, and the second memory device electrically connects to the logic device (this would be obvious that the second wafer with the first memory device would connect to the pixel array as the pixel array is above it, and the second wafer with the second memory device would connect to the logic device in the third wafer.).
Regarding claim 31, the combination of Choi and Lim teach:
Claim 31 is broader than claim 21, therefore, claim 31 is rejected for the same reasons as claim 21 above.
Regarding claim 32, the combination of Choi and Lim teach:
wherein the first memory device comprises: a first memory transistor (claim 21), horizontally adjacent to the pixel transistor array (any one of the transistors of Choi can be horizontally adjacent to the memory); and
a first MRAM unit, disposed vertically over and electrically connected to the first memory transistor (claims 24-25).
Regarding claim 33, the combination of Choi and Lim teach:
wherein the second memory device comprises: a second memory transistor, horizontally adjacent to the logic device; and a second MRAM unit, disposed vertically over and electrically connected to the second memory transistor (As taught by the combination of references in at least claims 26-27 the second memory device would comprise a second memory transistor horizontally adjacent to the logic device and be over the second memory transistor, as this is consistent with the duplication of wafer discussed in claim 21).
Regarding claim 34, the combination of Choi and Lim teach:
Claim 21 teaches all the limitations of claim 34 with the exception of:
a first bonding interface is defined between the first interconnect structure and the second interconnect structure;
a second bonding interface is defined between the second substrate and the third interconnect structure.
The combination of Choi and Lim teach:
a first bonding interface is defined between the first interconnect structure and the second interconnect structure; a second bonding interface is defined between the second substrate and the third interconnect structure (This would have been obvious based upon the teachings of Lim, where one would want the second and third substrate to be the same. Therefore, when one stacks the substrates on top of each other the limitations of this claim would be met. Additionally, it would have been obvious to try this bonding method as they are a limited number of combinations one can do with the interconnect structure on one side of a wafer and the transistors or image sensor on the other side of the wafer. Therefore, with limited options one of ordinary skill in the art would use routine skill in the art to optimize their recreation of the device of the Choi and Lim.).
Regarding claim 35, the combination of Choi and Lim teach:
at least a through via (Lim TSV2) penetrating the second substrate (332 of 300),
wherein the second interconnect structure and the third interconnect structure are electrically connected by the through via (through vias are well-known in the art. How to connected multiple wafers together by through vias is well-known in the art. While Choi and Lim may not expressly detail the limitations of the claim one of ordinary skill in the art using routine skill in the art would know how to create vias and metal lines to interconnect the wafers as claimed. This would require routine skill in the art).
Regarding claim 36, the combination of Choi and Lim teach:
wherein the through via contacts a metal line feature in a topmost metal line layer of the third interconnect structure at the second bonding interface (This limitation is obvious for the same reasons as claim 35 above.).
Regarding claim 37, the combination of Choi and Lim teach:
wherein a size of a layout of the first memory device is substantially equal to a size of a layout of the second memory device (while Choi and Lim may not expresely teach this limitation it would have been obvious to one of ordinary skill it the art to have the first and second memory device have the same layout. This is because it would further the motivation provide by Lim by making the manufacturing easier for the second and third wafer. This would further the motivation as it would simplify the processing of the sub-devices making up the final device.).
Regarding claims 38-40,
Claim 38 is rejected for the same reasons given in claim 21, 24-25, 28, and/or 31-33.
Conclusion
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/VINCENT WALL/ Primary Examiner, Art Unit 2898
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