Prosecution Insights
Last updated: July 17, 2026
Application No. 18/403,915

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103
Filed
Jan 04, 2024
Priority
Aug 18, 2023 — TW 112131182
Examiner
TORNOW, MARK W
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Siliconware Precision Industries Co., Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
578 granted / 748 resolved
+9.3% vs TC avg
Moderate +13% lift
Without
With
+13.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
25 currently pending
Career history
765
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
74.8%
+34.8% vs TC avg
§102
11.4%
-28.6% vs TC avg
§112
7.4%
-32.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 748 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Invention I, Claims 1-11, in the reply filed on 5/7/26 is acknowledged. The traversal is on the ground(s) that “the identified inventions pertain to a generic invention and are not mutually exclusive.” This is not found persuasive because that is not the standard for a product/method restriction and the Examiner has provided the required rationale in the restriction requirement of 3/11/26 – “Inventions I and Il are related as process of making and product made. The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). In the instant case, the product of Invention I as claimed can be made by another and materially different process than that of Invention Il as claimed, namely one in which the photonic component is grown directly on the electronic module rather than assembled from different pieces or additionally the module and component could be electrically connected after joining to the carrying structure rather than before.” The requirement is still deemed proper and is therefore made FINAL. Claims 12-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 5/7/26. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-4 and 7-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sekiguchi et al. (US Patent Application Publication No. 2015/0323738) (“Sekiguchi”). Regarding Claim 1, Sekiguchi teaches an electronic package (Figure 1A), comprising: a carrying structure (Figure 1A, item 150); an electronic module (Figure 1A, item 120) defined with a first connection area (Figure 1A, connection area where 131, 142, and 143 are present) and a second connection area (Figure 1A, connection area where items 141 are) separated from each other, wherein the electronic module is connected to the carrying structure via the first connection area (see Figure 1A, note 120 is connected to 150 through 131), and the second connection area protrudes from the carrying structure (see Figure 1A, note location of 141 is above the carrier structure 150 and thus “protrudes” from it); and a photonic component (Figure 1A, item 110, ¶0030) connected to the second connection area of the electronic module, wherein the photonic component and the carrying structure have a gap therebetween (see Figure 1A, note gap between 110 and 150). Regarding Claim 2, Sekiguchi further teaches the photonic component is externally connected to an optical fiber (see Figure 7A, note external connection of 210 to 301). Regarding Claim 3, Sekiguchi further teaches the electronic module is electrically connected to the carrying structure via a plurality of first conductive components (see Figure 1A, items 131) disposed on the first connection area, and the electronic module is electrically connected to the photonic component via a plurality of second conductive components disposed on the second connection area (Figure 1A, items 141). Regarding Claim 4, Sekiguchi further teaches a dimension of each of the first conductive components located in the first connection area is greater than a dimension of each of the second conductive components located in the second connection area (see Figure 1A, note the depicted difference in dimensions of elements 131 and 141). Regarding Claim 7, Sekiguchi further teaches the electronic module comprises an encapsulation layer (Figure 1A, item 130) having a first surface and a second surface opposing the first surface, a bridging component Figure 1A, item 131 on left side) embedded in the encapsulation layer, conductive pillars (Figure 1A, item 131 on right side) embedded in the encapsulation layer, a circuit structure (Figure 1A, item 120) disposed on the first surface of the encapsulation layer and electrically connected to the bridging component and the conductive pillars (see Figure 1A), and an electronic component disposed on and electrically connected to the circuit structure (see Figure 1A). Regarding Claim 8, Sekiguchi further teaches the electronic module comprises a plurality of the electronic components (see Figure 1B, item 121, ¶0037). Regarding Claim 9, Sekiguchi further teaches the plurality of electronic components are memory chips, electrical integrated circuit chips and switch dies (¶0037). Regarding Claim 10, Sekiguchi further teaches the electronic module further comprises a packaging layer covering the plurality of electronic components (¶0038). Regarding Claim 11, Sekiguchi further teaches in the electronic module, distances between side end surfaces of the plurality of electronic components and adjacent side surfaces of the packaging layer are different (see Figure 4 – note distances between side surfaces of the package are depicted differently). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sekiguchi as applied to Claim 1 above. Regarding Claim 5, Sekiguchi teaches Claim 1 as indicated above. Sekiguchi does not specifically teach the gap between the carrying structure and the photonic component is at least 100 µm, although a gap is clearly taught in Figure 1. However, absent a showing of criticality with respect to gap spacing (a result effective variable), it would have been obvious to a person of ordinary skill in the art at the time of the invention to adjust the thickness through routine experimentation in order to achieve optimized device package size. It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sekiguchi as applied to Claim 1 above, and further in view of Darmawikarta et al. (US Patent Application Publication No. 2023/0083222)(“Darmawikarta”). Regarding Claim 6, Sekiguchi teaches Claim 1 as indicated above. Sekiguchi does not specifically teach the carrying structure has a recess, and the photonic component is disposed in the recess of the carrying structure. However, Darmawikarta teaches including a recess in a carrier (Figure 1A, item 105) having an electronic chip (Figure 1A, item 130) and a photonic chip (Figure 1A, item 120) – see Figure 1A where 120 is recessed into 105. IT would have been obvious to a person having ordinary skill in the art at the time of effective filing to use the recess taught in Darmawikarta in the device of Sekiguchi, as doing so would decrease overall package height and the Examiner notes a change in shape of an element was considered a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (MPEP §2144.04) Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yang et al. (US Patent Application Publication No. 2022/0139894) Chang et al. (US Patent No. 10,930,628) Weng et al. (US Patent No. 11,614,592) Yen et al. (US Patent Application Publication No. 2023/0400648) Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK W TORNOW whose telephone number is (571)270-7534. The examiner can normally be reached M-Th 6:30-4:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MARK W. TORNOW Primary Examiner Art Unit 2891 /MARK W TORNOW/Primary Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Jan 04, 2024
Application Filed
Jun 29, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
90%
With Interview (+13.2%)
2y 10m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 748 resolved cases by this examiner. Grant probability derived from career allowance rate.

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