CTNF 18/403,930 CTNF 86178 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Invention II in the reply filed on 4/20/26 is acknowledged. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 8-15 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Jiang et al. (US Patent Application Publication No. 2023/0018716) (“Jiang”) . Regarding Claim 8, Jiang teaches a method of forming a memory device (see Figure 7), the method comprising: forming a plurality of memory cell units (see Figure 7), each unit comprising a plurality of memory cells arranged in at least two layers (see Figure 7, note multiple layers depicted in the z direction), each layer having a grid pattern (see grid pattern depicted in Figure 7), each layer having a wordline (Figure 7, items 121) extending from the plurality of memory cells in a first direction, each memory cell unit having a vertical bitline (Figure 7, item 160) extending along a third direction and located adjacent the memory cell unit along a second direction, and horizontal bitlines over the memory cell units (see Figure 6), the horizontal bitlines in electrical connection with one vertical bitline on a side of the memory cell unit (see Figure 6 and associated text). Regarding Claim 9, Jiang further teaches each of the memory cells in a layer are connected to the same wordline (Figure 7, item 120). Regarding Claim 10, Jiang further teaches the wordlines form a staircase pattern with a surface accessible along the third direction (see Figure 7). Regarding Claim 11, Jiang further teaches forming a wordline contact extending in the third direction from the surface accessible along the third direction (see Figure 7). Regarding Claim 12, Jiang further teaches bitline contacts extending in the third direction from a surface of the horizontal bitlines (see Figure 7 and note shapes of 160). Regarding Claim 13, Jiang teaches a method of forming a memory device, the method comprising: selectively recessing SiGe (¶0094) layers of a plurality of layer stacks through wordline openings formed adjacent a memory region, the layer stacks comprising alternating layers of SiGe and silicon (¶0091-0096), the silicon layers alternating between a thin layer and a thick layer (see Figure 9), the plurality of layer stacks spaced apart in a first direction with each layer extending along a second direction and the layers stacked in a third direction (see Figure 9), a height of the layer stacks decreasing along the first direction with a tallest stack closest to the memory region (see Figure 21); recessing the silicon layers to remove the thin layers and reduce a thickness of the thick layers to leave a layer stack with spaced silicon layers (see Figure 13); forming a dielectric layer between the spaced silicon layers (see Figure 14); removing the spaced silicon layers from the layer stack to leave spaced dielectric layers (see Figure 23); and forming wordlines by depositing a metal layer between the spaced dielectric layers to form a layer stack having alternating dielectric layers and wordlines comprising metal layers (see Figure 24), the wordlines extending outward from the memory region in a staircase pattern (see Figure 24). Regarding Claim 14, Jiang further teaches forming wordline contacts along the third direction to contact the wordlines (see Figure 24). Regarding Claim 15, Jiang further teaches forming horizontal bitlines above the memory region, the horizontal bitlines contacting vertical bitlines within the memory region (see Figure 7, items 160) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al. (US Patent No. 11,367,726) Kim et al. (US Patent Application Publication No. 2020/0279601) Kim et al. (US Patent Application Publication No. 2020/0227418) Kim et al. (US Patent Application Publication No. 2020/0111793) Lee et al. (US Patent No. 10,504,901) Sonehara et al. (US Patent No. 9,704,801) Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK W TORNOW whose telephone number is (571)270-7534. The examiner can normally be reached M-Th 6:30-4:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MARK W. TORNOW Primary Examiner Art Unit 2891 /MARK W TORNOW/Primary Examiner, Art Unit 2891 Application/Control Number: 18/403,930 Page 2 Art Unit: 2891 Application/Control Number: 18/403,930 Page 3 Art Unit: 2891 Application/Control Number: 18/403,930 Page 4 Art Unit: 2891 Application/Control Number: 18/403,930 Page 5 Art Unit: 2891
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