DETAILED ACTION
This correspondence is in response to the communications received June 16, 2026. Claims 1-15 and 21-25 are pending. Claims 16-20 have been cancelled. Claims 21-25 have been newly added.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II method claims in the reply filed on June 16, 2026 is acknowledged.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 3-5, a method for manufacturing a semiconductor device, comprising:
forming a semiconductor structure (1) including a metal gate feature (121, ¶ 0025);
forming an etch stop layer (14, ¶ 0025) on the semiconductor structure (on 1);
forming a first dielectric layer (15) on the etch stop layer (on 14) opposite to the semiconductor structure (other side of 1 from 14),
the etch stop layer being made of a dielectric material different from a dielectric material of the first dielectric layer (materials for 15 discussed in ¶ 0026, material for 14 discussed in ¶ 0025, this limitation is only present in these originally filed claims, some of the materials listed are the same, so the support is only really here in this claim limitation.);
forming a trench (20, ¶ 0032) that penetrates the first dielectric layer and the etch stop layer so as to expose an upper surface of the metal gate feature (20 penetrates 14 and 15, to expose top of 121, ¶ 0032);
conformally forming a liner material film (21’, ¶ 0033) on the first dielectric layer (on sidewalls of 15), a trench-defining wall that defines the trench (19a), and the upper surface of the metal gate feature (upper surface of 121); and
forming a via contact material (22’) on the liner material film (on 21’), such that the trench (20) is filled by the liner material film (21’) and the via contact material (22’).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 10 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. (US 2024/0290864) in view of Lin et al. (US 2022/0352328).
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Regarding claim 1, the prior art of Ho discloses in Figs. 14, 15 and 16A, a method for manufacturing a semiconductor device (see ¶ 0010, “A stacking transistor, such as a CFET, and the method of forming the same are provided.”, ¶ 0030, “The semiconductor fins and the nanostructures may be patterned by any suitable method.”), comprising:
forming a semiconductor structure (Many features constitute the transistor device, including, “semiconductor nanostructures 26 act as the channel regions for the nanostructure-FETs.”, ¶ 0013, which is the channel) including a metal gate feature (¶ 0047, “gate electrodes 80L may be formed of a metal-containing material such as …”);
forming an etch stop layer (“ESL 126”, ¶ 0063, where “ESL” is an acronym for “etch stop layer”, see ¶ 0010, “etch stop layer (ESL)”) on the semiconductor structure (on 26);
forming a first dielectric layer (“ILD 128”, ¶ 0063) on the etch stop layer (128 on 126 opposite to 26) opposite to the semiconductor structure (128 is on side of 126 opposite position of 26),
the etch stop layer being made of a dielectric material different from a dielectric material of the first dielectric layer (126 is the etch stop layer (ESL) and 128 is the interlevel dielectric (ILD), where in ¶ 0041, “A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed over the lower epitaxial source/drain regions 62L. The first CESL 66 may be formed of a dielectric material having a high etching selectivity from the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which may be formed by any suitable deposition process, such as CVD, ALD, or the like. The first ILD 68 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The applicable dielectric material of the first ILD 68 may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), silicon oxide, or the like.”, discusses the different materials used for the ILD in contrast to etch stop layers.);
forming a trench that penetrates the first dielectric layer and the etch stop layer so as to expose an upper surface of the metal gate feature (top of 80L is exposed by opening 130, ¶ 0067, where 130 is an opening in at least layers 126 and 128);
forming a film (“gate contacts 132 … The conductive material may be cobalt, tungsten, copper, a copper alloy, silver, gold, aluminum, nickel”) on the first dielectric layer (on inner wall of 128), a trench-defining wall that defines the trench (wall that defines 130), and the upper surface of the metal gate feature (upper surface of 80L); and
the trench is filled by the film (130 is filled by 132).
Ho discloses the potential use of a liner with the conductive fill material in the trench (see ¶ 0068, “As an example to form the backside gate contacts 132, a liner (not separately illustrated), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the backside gate contact openings 130.”), but as it is not shown in the drawings, the following reference will be used to disclose these features.
Ho does not disclose,
“conformally forming a liner material film on the first dielectric layer, a trench-defining wall that defines the trench, and the upper surface of the metal gate feature; and
forming a via contact material on the liner material film, such that the trench is filled by the line material film and the via contact material.”
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The prior art of Lin discloses in Figs. 2Q-2S,
conformally forming a liner material film (¶ 0086, 166 is both a liner and conformal by the nature of it’s orientation with respect to opening 165) on the first dielectric layer (“filling layer 160 is made of silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), dielectric material(s) with low dielectric constant (low-k),”, ¶ 0078), a trench-defining wall that defines the trench (wall shown in Fig. 2R of opening 165), and the upper surface of the metal gate feature (“gate structures 140”, ¶ 0057, formed from “layers 144 are made of a conductive material, such as tungsten (W)”, and “138 is made of conductive material, such as aluminum (Al), copper (Cu), tungsten (W) …”, ¶ 0048); and
forming a via contact material (layer 168, “a barrier layer 166 and a conductive layer 168 are formed in the via hole 165 to form a gate contact structure 170”, ¶ 0082) on the liner material film (on 166), such that the trench (165) is filled by the line material film and the via contact material (165 filled with both of 166 and 168).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of,
“conformally forming a liner material film on the first dielectric layer, a trench-defining wall that defines the trench, and the upper surface of the metal gate feature; and
forming a via contact material on the liner material film, such that the trench is filled by the line material film and the via contact material.”, as disclosed by Lin in the system of Ho, for the purpose of improving the electrical contact in the aspects of adhesion, diffusion barrier or improved conductivity. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Ho et al. disclose the method as claimed in claim 1, and Ho discloses in Figs. 14-16A, wherein the semiconductor structure further includes a second dielectric layer (“ILD 124”, ¶ 0063) which is disposed below the etch stop layer (previously identified 126) opposite to the first dielectric layer (previously identified 128) and which is made of a dielectric material different from the dielectric material of the etch stop layer (¶ 0041 discloses where the etch stop layers are made of different materials than the ILD layers); and the trench further penetrates the second dielectric layer (Ho’s 130 penetrates 124 in Fig. 15).
Regarding claim 10, the prior art of Ho discloses in Figs. 14, 15 and 16A, a method for manufacturing a semiconductor device (see ¶ 0010, “A stacking transistor, such as a CFET, and the method of forming the same are provided.”, ¶ 0030, “The semiconductor fins and the nanostructures may be patterned by any suitable method.”), comprising:
forming a semiconductor structure (Many features constitute the transistor device, including, “semiconductor nanostructures 26 act as the channel regions for the nanostructure-FETs.”, ¶ 0013, which is the channel) including a metal gate feature (¶ 0047, “gate electrodes 80L may be formed of a metal-containing material such as …”) and a first dielectric layer covering the metal gate feature (“ILD 124”, ¶ 0063, which covers top of 80L, where “ILD” stands for “dielectric material”, ¶ 0041);
forming an etch stop layer (“ESL 126”, ¶ 0063, where “ESL” is an acronym for “etch stop layer”, see ¶ 0010, “etch stop layer (ESL)”) on the first dielectric layer (126 on 124);
forming a second dielectric layer (“ILD 128”, ¶ 0063) on the etch stop layer opposite to the first dielectric layer (128 on 126, opposite to 124), the etch stop layer (126) being made of a dielectric material different from a dielectric material of the first dielectric layer or a dielectric material of the second dielectric layer (¶ 0041, “A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed over the lower epitaxial source/drain regions 62L. The first CESL 66 may be formed of a dielectric material having a high etching selectivity from the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which may be formed by any suitable deposition process, such as CVD, ALD, or the like. The first ILD 68 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The applicable dielectric material of the first ILD 68 may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), silicon oxide, or the like.”, discusses the different materials used for the ILD in contrast to etch stop layers.);
forming a trench (“gate contact openings 130”, ¶ 0065) that penetrates the second dielectric layer, the etch stop layer, and the first dielectric layer so as to expose an upper surface of the metal gate feature (130 penetrates 128, 126, 124 to expose top surface of 80L, see Fig. 15); and
forming a metal gate via (“gate contacts 132 … conductive material may be cobalt, tungsten, copper, a copper alloy, silver, gold, aluminum, nickel”, ¶ 0068) in the trench (in 130 in Fig. 16A) so as to be connected to the metal gate feature (132 connects to 80L), the metal gate via including a liner and a via contact covered by the liner (“to form the backside gate contacts 132, a liner (not separately illustrated), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the backside gate contact openings 130.”, ¶ 0068).
Ho does not explicitly disclose in the drawings, “the metal gate via including a liner and a via contact covered by the liner”.
The prior art of Lin discloses in Figs. 2Q-2S, the metal gate via (“a gate contact structure 170”, ¶ 0082) including a liner (“barrier layer 166”, ¶ 0082) and a via contact (“conductive layer 168”, ¶ 0082) covered by the liner (166 covers outer lower and lateral surfaces of 168).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of, “the metal gate via including a liner and a via contact covered by the liner”, as disclosed by Lin in the system of Ho, for the purpose of improving the electrical contact in the aspects of adhesion, diffusion barrier or improved conductivity. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 21, the prior art of Ho discloses in Figs. 14, 15 and 16A, a method for manufacturing a semiconductor device (see ¶ 0010, “A stacking transistor, such as a CFET, and the method of forming the same are provided.”, ¶ 0030, “The semiconductor fins and the nanostructures may be patterned by any suitable method.”), comprising:
forming a semiconductor structure (Many features constitute the transistor device, including, “semiconductor nanostructures 26 act as the channel regions for the nanostructure-FETs.”, ¶ 0013, which is the channel) including a metal gate feature (¶ 0047, “gate electrodes 80L may be formed of a metal-containing material such as …”) and a first dielectric layer disposed on the metal gate feature (“ILD 124”, ¶ 0063, which covers top of 80L, where “ILD” stands for “dielectric material”, ¶ 0041);
forming an etch stop layer (“ESL 126”, ¶ 0063, where “ESL” is an acronym for “etch stop layer”, see ¶ 0010, “etch stop layer (ESL)”) on the semiconductor structure (on 26);
forming a second dielectric layer (“ILD 128”, ¶ 0063) on the etch stop layer (on 126) opposite to the semiconductor structure (opposite to 26), the etch stop layer (126) being made of a dielectric material different from a dielectric material of the second dielectric layer (¶ 0041, “A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed over the lower epitaxial source/drain regions 62L. The first CESL 66 may be formed of a dielectric material having a high etching selectivity from the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which may be formed by any suitable deposition process, such as CVD, ALD, or the like. The first ILD 68 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The applicable dielectric material of the first ILD 68 may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), silicon oxide, or the like.”, discusses the different materials used for the ILD in contrast to etch stop layers.); and
forming a metal gate via (“gate contacts 132 … conductive material may be cobalt, tungsten, copper, a copper alloy, silver, gold, aluminum, nickel”, ¶ 0068) to penetrate the second dielectric layer, the etch stop layer and the first dielectric layer (132 penetrates 128, 126 and 124), and to terminate at the metal gate feature (132 terminates at top surface of 80L), the metal gate via including a liner and a via contact that is covered by the liner (“to form the backside gate contacts 132, a liner (not separately illustrated), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the backside gate contact openings 130.”, ¶ 0068) and that is electrically connected to the metal gate feature (132 is in direct contact with 80L).
Ho does not explicitly disclose in the drawings, “the metal gate via including a liner and a via contact that is covered by the liner and that is electrically connected to the metal gate feature.”
The prior art of Lin discloses in Figs. 2Q-2S, the metal gate via (“a gate contact structure 170”, ¶ 0082) including a liner (“barrier layer 166”, ¶ 0082) and a via contact (“conductive layer 168”, ¶ 0082) that is covered by the liner (166 covers outer lower and lateral surfaces of 168) and that is electrically connected to the metal gate feature (170 is in contact with equivalent “metal gate feature”, which are 144 and 138, “the protection layers 144 are made of a conductive material, such as tungsten (W) … gate electrode layers 138”, ¶ 0057).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of, “the metal gate via including a liner and a via contact that is covered by the liner and that is electrically connected to the metal gate feature.”, as disclosed by Lin in the system of Ho, for the purpose of improving the electrical contact in the aspects of adhesion, diffusion barrier or improved conductivity. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. (US 2024/0290864) in view of Lin et al. (US 2022/0352328) in view of Liang et al. (US 2024/0313075).
Regarding claim 3, the prior art of Ho et al. disclose the method as claimed in claim 1, however Ho does not disclose, “further comprising, after formation of the liner material film and before formation of the via contact material, removing a portion of the liner material film in contact with the upper surface of the metal gate feature, so as to expose the upper surface of the metal gate feature”.
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Liang discloses in Fig. 12A, further comprising, after formation of the liner material film (“barrier layer 232”, ¶ 0033) and before formation of the via contact material (232 formed in step of Fig. 8A to 9A, then 234b is formed later in Figs. 10A to 11A), removing a portion of the liner material film in contact with the upper surface of the metal gate feature, so as to expose the upper surface of the metal gate feature (“The trenches 230a and 230b may be lined with a barrier layer 232 along sidewalls of the trenches. The barrier layer is a dielectric barrier layer formed by a suitable procedure that includes deposition and anisotropic etch (e.g., plasma etch) to remove the deposited barrier layer on bottom surface of the trenches.”, ¶ 0033).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of, “further comprising, after formation of the liner material film and before formation of the via contact material, removing a portion of the liner material film in contact with the upper surface of the metal gate feature, so as to expose the upper surface of the metal gate feature”, as disclosed by Liang in the system of Ho, for the purpose of improving the electrical contact in the aspects of adhesion, diffusion barrier or improved conductivity. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 4, the prior art of Ho et al. disclose the method as claimed in claim 3, wherein the portion of the liner material film is removed by a plasma etching process (Liang discloses, “The trenches 230a and 230b may be lined with a barrier layer 232 along sidewalls of the trenches. The barrier layer is a dielectric barrier layer formed by a suitable procedure that includes deposition and anisotropic etch (e.g., plasma etch) to remove the deposited barrier layer on bottom surface of the trenches.”, ¶ 0033).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. (US 2024/0290864) in view of Lin et al. (US 2022/0352328) in view of Liang et al. (US 2024/0313075) in view of Kao et al. (US 2025/0081527).
Regarding claim 5, the prior art of Ho et al. disclose the method as claimed in claim 4, however Ho does not disclose, “wherein the plasma etching process is conducted using a gas that includes argon gas, helium gas, hydrogen gas, neon gas, titanium chloride gas, boron trichloride gas, chlorine gas, nitrogen gas, oxygen gas, hexafluorobutadiene gas, octafluorocyclobutane gas, carbon tetrafluoride gas, fluoromethane gas, trifluoromethane gas, sulfur hexafluoride gas, sulfur dioxide gas, or combinations thereof.”
Kao discloses in ¶ 0040 the use of a plasma etching gas includes argon, ¶ 0040.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of, “wherein the plasma etching process is conducted using a gas that includes argon gas, helium gas, hydrogen gas, neon gas, titanium chloride gas, boron trichloride gas, chlorine gas, nitrogen gas, oxygen gas, hexafluorobutadiene gas, octafluorocyclobutane gas, carbon tetrafluoride gas, fluoromethane gas, trifluoromethane gas, sulfur hexafluoride gas, sulfur dioxide gas, or combinations thereof.”, as disclosed by Kao in the system of Ho, for the purpose of adjusting etch rates to allow for efficient and complete material removal. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 6, the prior art of Ho et al. disclose the method as claimed in claim 5, and Kao discloses, wherein a gas flow rate of the gas used in the plasma etching process ranges from 5 sccm to 1000 sccm, and a plasma generation power used in the plasma etching process ranges from 1 W to 2000 W (both flow rate and power ranges disclosed in ¶ 0040).
Claims 8, 9, 11-15 and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. (US 2024/0290864) in view of Lin et al. (US 2022/0352328) in view of Liang et al. (US 2024/0313075).
Regarding claim 8, the prior art of Ho et al. disclose the method as claimed in claim 1, however Ho does not disclose, “further comprising, after formation of the via contact material, conducting a planarization process to remove an excess portion of the via contact material and an excess portion of the liner material film, so as to form the via contact material into a via contact and to form the liner material film into a liner.”
Liang discloses in Figs. 23A-24A, further comprising, after formation of the via contact material, conducting a planarization process to remove an excess portion of the via contact material and an excess portion of the liner material film, so as to form the via contact material into a via contact and to form the liner material film into a liner (“gate vias 234b interfacing with metal gates 210. Now in reference to FIG. 24A, the vias 234 are planarized such that top surfaces of the vias 234 are coplanar with the top surface of the ILD layer 228.”, ¶ 0063).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of, “further comprising, after formation of the via contact material, conducting a planarization process to remove an excess portion of the via contact material and an excess portion of the liner material film, so as to form the via contact material into a via contact and to form the liner material film into a liner.”, as disclosed by Liang in the system of Ho, for the purpose of removing the excess metal material to disconnect the plural electrical connection vias so they do not short circuit and are separated so they can operate in their respective functional roles. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 9, the prior art of Ho et al. disclose the method as claimed in claim 8, and Liang discloses in Fig. 22A, 24A, wherein a percentage of an area of the trench-defining wall of the trench covered by the liner based on a total surface area of the trench-defining wall is greater than 0% and up to 100% (232 covers the entire surface area of the sidewalls of the opening 230b).
Regarding claim 11, the prior art of Ho et al. disclose the method as claimed in claim 10.
First, Ho does not explicitly disclose in the drawings,
“wherein formation of the metal gate via includes:
conformally forming a liner material film on the second dielectric layer, a trench-defining wall that defines the trench, and the upper surface of the metal gate feature;
forming a via contact material on the liner material film and in the trench, such that the trench is filled by the via contact material;”.
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The prior art of Lin discloses in Figs. 2Q-2S,
“wherein formation of the metal gate via (“gate contact structure 170”, ¶ 0082) includes:
conformally forming a liner material film (¶ 0086, 166 is both a liner and conformal by the nature of it’s orientation with respect to opening 165) on the second dielectric layer (“ILD layer 164”, ¶ 0089), a trench-defining wall that defines the trench (166 in the opening 165 and on the walls of the opening which are the walls of materials that end at the opening), and the upper surface of the metal gate feature (166 on top of portion 144 of gate, ¶ 0057, “protection layers 144 are made of a conductive material, such as tungsten (W). The protection layers 144 are electrically connected to the gate electrode layers 138 of the gate structures 140.”);
forming a via contact material (“conductive layer 168”, ¶ 0087) on the liner material film (168 on 166) and in the trench (in “via hole 165”, ¶ 0081), such that the trench (165) is filled by the via contact material (165 filled with 168);”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of,
“wherein formation of the metal gate via includes:
conformally forming a liner material film on the second dielectric layer, a trench-defining wall that defines the trench, and the upper surface of the metal gate feature;
forming a via contact material on the liner material film and in the trench, such that the trench is filled by the via contact material;”, as disclosed by Lin in the system of Ho, for the purpose of improving the electrical contact in the aspects of adhesion, diffusion barrier or improved conductivity. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Ho does not disclose, “removing an excess portion of the via contact material and an excess portion of the liner material film, so as to obtain the metal gate via.”
Liang discloses in Figs. 23A-24A, removing an excess portion of the via contact material and an excess portion of the liner material film, so as to obtain the metal gate via (“gate vias 234b interfacing with metal gates 210. Now in reference to FIG. 24A, the vias 234 are planarized such that top surfaces of the vias 234 are coplanar with the top surface of the ILD layer 228.”, ¶ 0063).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of, “removing an excess portion of the via contact material and an excess portion of the liner material film, so as to obtain the metal gate via.”, as disclosed by Liang in the system of Ho, for the purpose of removing the excess metal material to disconnect the plural electrical connection vias so they do not short circuit and are separated so they can operate in their respective functional roles. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 12, the prior art of Ho et al. disclose the method as claimed in claim 11, and Lin discloses in Figs. 2S, wherein after removal of the excess portion of the via contact material and the excess portion of the liner material film (as disclosed by Liang discloses in Figs. 23A-24A in the rejection of claim 11), the via contact material (168 of Lin in Fig. 2S) is formed into the via contact (top portion of 168 is coplanar with top of 164, formed into 168’s final structural form), and the liner material film is formed into the liner (top portion of 166 is coplanar with top of 164, formed into 166’s final structural form), the liner including a lower liner portion and an upper liner portion extending upwardly from the lower liner portion (166 has upward extending portions and a horizontal portion), the lower liner portion being disposed between the via contact and the upper surface of the metal gate feature (horizontal portion of 166 between 144 and 168), the upper liner portion laterally covering the via contact (upward extending portions of 166 cover sidewalls of 168).
Regarding claim 13, the prior art of Ho et al. disclose the method as claimed in claim 11, however Ho does not disclose,
“further comprising, after formation of the liner material film and before formation of the via contact material, removing a portion of the liner material film in contact with the upper surface of the metal gate feature.”
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Liang discloses in Fig. 12A,
further comprising, after formation of the liner material film (“barrier layer 232”, ¶ 0033) and before formation of the via contact material (232 formed in step of Fig. 8A to 9A, then 234b is formed later in Figs. 10A to 11A), removing a portion of the liner material film in contact with the upper surface of the metal gate feature (“The trenches 230a and 230b may be lined with a barrier layer 232 along sidewalls of the trenches. The barrier layer is a dielectric barrier layer formed by a suitable procedure that includes deposition and anisotropic etch (e.g., plasma etch) to remove the deposited barrier layer on bottom surface of the trenches.”, ¶ 0033).”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of, “further comprising, after formation of the liner material film and before formation of the via contact material, removing a portion of the liner material film in contact with the upper surface of the metal gate feature.”, as disclosed by Liang in the system of Ho, for the purpose of improving the electrical contact in the aspects of adhesion, diffusion barrier or improved conductivity. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 14, the prior art of Ho et al. disclose the method as claimed in claim 13, wherein after removal of the excess portion of the via contact material and the excess portion of the liner material film (as disclosed by Liang discloses in Figs. 23A-24A in the rejection of claim 11), the via contact material is formed into the via contact (Liang, Fig. 24A, shows top portion of 234b, ¶ 0033, is coplanar with top of 228, formed into 234b’s final structural form), and the liner material film is formed into the liner (top portion of 232 is coplanar with top of 228, formed into 232’s final structural form), the via contact being in direct contact with the metal gate feature (234b in direct contact with “metal gate 210”, ¶ 0022, seen identified in Fig. 23A) and being laterally covered by the liner (234b has sidewalls covered by 232).
Regarding claim 15, the prior art of Ho et al. disclose the method as claimed in claim 13, and Ho teaches in Figs. 15-16A, wherein the trench (“gate contact openings 130”, ¶ 0065) is formed to further extend into an upper gate portion of the metal gate feature (130 vertically passes below the top most surface of “gate electrode 80L”, ¶ 0014).
Regarding claim 22, the prior art of Ho et al. disclose the method as claimed in claim 21, however Ho does not disclose in the drawings explicitly,
“wherein the liner includes a lower liner portion disposed on the metal gate feature and covering a bottom surface of the via contact, and an upper liner portion extending upwardly from the lower liner portion and covering a lateral surface of the via contact.”
Lin discloses in Figs. 2S,
wherein the liner (¶ 0086, 166 is a liner by the nature of it’s orientation with respect to opening 165) includes a lower liner portion disposed on the metal gate feature (horizontal portion of 166 on portion 144 of 140, “protection layers 144 are made of a conductive material, such as tungsten (W). The protection layers 144 are electrically connected to the gate electrode layers 138 of the gate structures 140.”, ¶ 0057) and covering a bottom surface of the via contact (166 covers the bottom surface of “conductive layer 168”, ¶ 0082), and an upper liner portion extending upwardly from the lower liner portion and covering a lateral surface of the via contact (upward extending portions of 166 cover sidewalls of 168).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of,
“wherein the liner includes a lower liner portion disposed on the metal gate feature and covering a bottom surface of the via contact, and an upper liner portion extending upwardly from the lower liner portion and covering a lateral surface of the via contact.”, as disclosed by Lin in the system of Ho, for the purpose of improving the electrical contact in the aspects of adhesion, diffusion barrier or improved conductivity. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 23, the prior art of Ho et al. disclose the method as claimed in claim 21, however Ho does not disclose in the drawings explicitly,
“wherein the liner covers a lateral surface of the via contact, and the via contact is in direct contact with the metal gate feature.”
Liang discloses in Fig. 11A,
wherein the liner (“barrier layer 232”, ¶ 0033) covers a lateral surface of the via contact (232 covers lateral surface of “gate vias 234b”, ¶ 0033), and the via contact (234b) is in direct contact with the metal gate feature (234b is in direct contact with “metal gates 210”, identified in Fig. 10A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of, “wherein the liner covers a lateral surface of the via contact, and the via contact is in direct contact with the metal gate feature.”, as disclosed by Liang in the system of Ho, for the purpose of improving the electrical contact in the aspects of adhesion, diffusion barrier or improved conductivity. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 24, the prior art of Ho et al. disclose the method as claimed in claim 21, however Ho does not disclose explicitly, “wherein the liner and the via contact are made of a same material.”
Lin discloses in ¶ 0085 and 0086, where the liner 166 can be several same metal material types as the conductive fill 168.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of, “wherein the liner and the via contact are made of a same material.”, as disclosed by Lin in the system of Ho, for the purpose of improving the electrical connection’s adhesion, improved conductivity and compatibility between the materials. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. (US 2024/0290864) in view of Lin et al. (US 2022/0352328) in view of Liang et al. (US 2024/0313075) in view of Omura et al. (US 2007/0210350).
Regarding claim 25, the prior art of Ho et al. disclose the method as claimed in claim 21, and Ho discloses in Fig. 15,
further comprising, before formation of the metal gate via (via not yet in place by Fig. 15), forming a trench (“gate contact openings 130”, ¶ 0065) that is to be filled with the metal gate via (130 filled by “gate contacts 132”, by process step shown in Fig. 16A), and that penetrates the second dielectric layer (“ILD 128”, ¶ 0063), the etch stop layer (“ESL 126”, ¶ 0063), and the first dielectric layer (“ILD 124”, ¶ 0063) so as to expose the metal gate feature (top surface of “gate electrode 80L”, ¶ 0014).
Ho does not disclose, “wherein the trench has an aspect ratio ranging from 3 to 8”.
Omura discloses in ¶ 0170, “gate plug 33) preferably has an aspect ratio of e.g. 5 to 10.” In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of, “wherein the trench has an aspect ratio ranging from 3 to 8”, as disclosed by Omura in the system of Ho, for the purpose of improving the electrical connection by aiding the via fill process by the geometry of the via to improve quality of fill. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of Liang et al. (US 2024/0313075) discloses in Fig. 9B-12B, where a liner (232) fills an opening (230b) and exposes top of gate (210), but does not disclose the liner’s geometry as claimed in claim 7.
“7. (Original) The method as claimed in claim 4, wherein, after removal of the portion of the liner material film, a portion of the liner material film remains to cover the trench-defining wall and includes an upper part and a lower part that is connected between the upper part and the metal gate feature, the upper part having a thickness smaller than a thickness of the lower part.”
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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