DETAILED ACTION
This correspondence is in response to the communications received May 11, 2026. Claims 18-37 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant has made no claim to the benefit of an earlier filing date.
Election/Restrictions
Applicant’s election without traverse of Group II, Species I in the reply filed on May 11, 2026 is acknowledged. Claims 18-37 have been newly submitted. Claims 23 and 31 have been withdrawn from consideration for the following reasons.
“23. (New) The method as claimed in claim 22, wherein a dimension of the top electrode along a horizontal direction is smaller than dimensions of the switching layer, the auxiliary layer and the bottom electrode.” This claim is directed to a non-elected embodiment of Fig. 20, and therefore is now withdrawn from examination.
“31. (New) The method as claimed in claim 25, wherein the auxiliary film is formed after forming the bottom electrode layer and after forming the resistance switching film.” This claim is directed to an embodiment that is not the elected embodiment of Fig. 26, and therefore is now withdrawn from examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 31 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The recitation, wherein the auxiliary film is formed after forming the bottom electrode layer and after forming the resistance switching film”, renders the claim indefinite, as claim 25 places the location of the auxiliary layer under the switching film, see last three lines of claim 25. This limitation relocates the auxiliary film (which has been established as being under the switching layer) to a position above the switching layer. This would cause the location of the auxiliary film to be unclear due to the conflicting nature of the claims.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 2 (shown for element identification), 11, 12 and Fig. 26, a method for manufacturing a semiconductor device, comprising:
forming a bottom electrode layer (20) over a substrate (30) that includes a lower interlayer dielectric (ILD) layer (111) and a lower wire (11) within the lower ILD layer (in 111);
forming an auxiliary film (22, which is disclosed to be ruthenium nitride, ¶ 0018), a resistance switching film (24) and a top electrode layer (26) over the bottom electrode layer (20),
wherein the auxiliary film (22) is formed between the resistance switching film layer and one of the bottom electrode layer and the top electrode layer (22 between 20 and 26), and the top electrode layer (26) is formed over the auxiliary film (over 22) and the resistance switching film (over 24);
forming a hard mask (82) on the top electrode layer (on 26) and overlying the lower wire (over 20); and
performing at least one etch process (step shown in Fig. 11 to 12) to etch into the top electrode layer (26, which is where analogous layer 780 is patterned to individual cell stack including 78), the resistance switching film (24, which is where analogous layer 760 is patterned to individual cell stack including 76), the auxiliary film (22, which is where analogous layer 740 is patterned to individual cell stack including 74) and the bottom electrode layer (20, which is where analogous layer 720 is patterned to individual cell stack including 72) with the hard mask in place (82 is deposited at some point after Fig. 11, then a patterning etch creates the structure shown in Fig. 12,), so as to form a top electrode (78/26), a switching layer (76/24), an auxiliary layer (74/22) and a bottom electrode (72/20).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18, 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2016/0087199) in view of Lu et al. (US 2022/0310624) in view of Kim et al. (US 2014/0287535).
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Regarding claim 18, the prior art of Jang discloses in Fig. 2 and 9A (shown below in the rejection of claim 1), a method for manufacturing a semiconductor device (forming a memory device on a semiconductor substrate, ¶ 0008), comprising:
forming a bottom electrode layer (208b1, “the first electrode 208b of the resistive random access memory device 500b is a stacked structure including a metal nitride layer 208b1”, ¶ 0034) over a substrate (“semiconductor substrate 200”, ¶ 0028) that includes a lower interlayer dielectric (ILD) layer (“interlayer dielectric layer 204”, ¶ 0028) and a lower wire (“first electrode contact plug 206 may include tungsten (W)”, ¶ 0028) within the lower ILD layer (206 in 204);
forming an auxiliary film (208b3, “metal nitride layer 208b3”, ¶ 0034), a resistance switching film (210, “resistive switching layer 210”, ¶ 0034) and a top electrode layer (212, “second electrode 212”, ¶ 0034) over the bottom electrode layer (208b3, 210, 212 all three on 208b1),
wherein the auxiliary film (208b3) is formed between the resistance switching film layer (210) and one of the 1) bottom electrode layer (208b1) and 2) the top electrode layer (the other option shown by Jang), and
the top electrode layer (212) is formed over the auxiliary film (over 208b3) and the resistance switching film (over 210);
forming a hard mask (214 is a silicon nitride layer, which is conventionally known as a “hard mask”, however Jang does not use this term explicitly, “the barrier liner layer 214 may comprise silicon nitride”, ¶ 0043. Separately, an actually stated “hard mask” is used in the patterning etch step in Fig. 9A, the feature “hard mask pattern 230”, ¶ 0051) on the top electrode layer (on 212) and overlying the lower wire (overlying the lower wire 206); and
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performing at least one etch process to etch into the top electrode layer, the resistance switching film, the auxiliary film and the bottom electrode layer with the hard mask in place (as discussed below the hard mask is used to mask the etchant to pattern the active layer stack), so as to form a top electrode, a switching layer, an auxiliary layer and a bottom electrode (“Referring to FIG. 9A, a lithography process and an etching process is performed to form a hard mask pattern 230 on the second electrode material layer 212a. Then, the hard mask pattern 230 is used as a mask, and an etching process is performed to remove the second electrode material layer 212a, the resistive switching material layer 210a, and the stacked structure composed of the metal nitride material layer 308b1, the metal oxide material layer 308b2 and the metal nitride material layer 308b3 which are not covered by the hard mask pattern 230, so as to form the metal-insulator-metal stacked layer 250b composed of the second electrode 212, the resistive switching layer 210 and first electrode 208b (including the metal nitride layer 208b1, the metal oxide material layer 208b2 and the metal nitride material layer 208b3) as shown in FIG. 2.”, ¶ 0051. It is noted that element 308b1 is analogous to 208b1, 208b3 is analogous to 308b3, 210a is analogous to 210, 212a is analogous to 212. Therefore, this etch patterning step is used to make the resulting structure of Fig. 2.).
First, Jang does not disclose wherein the metal nitride layer is an “auxiliary film”.
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Lu discloses in Figs. 1 and 2, and ¶ 0051, “With reference to FIG. 1, in some embodiments of this disclosure, the second conductive block 32 can include a conductive auxiliary layer 321 and a conductive plug 322. The conductive auxiliary layer 321 covers the top end of the first conductive block 31, the chamfered structure 311, and the transition wall 312, and covers a sidewall of the contact hole 40. The conductive plug 322 is formed on the conductive auxiliary layer 321 and fills the contact hole 40. The conductive auxiliary layer 321 is configured to block the conductive plug 322 and the first conductive block 31 from interpenetrating.”, and ¶ 0052, “A material of the conductive auxiliary layer 321 can include titanium nitride, etc.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate “an auxiliary layer”, as disclosed by Lu in the system of Jang, for the purpose of providing a barrier metal layer that can prevent migration atoms from of neighboring material layers. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Jang does not disclose, “forming a hard mask on the top electrode layer and overlying the lower wire”, where the “hard mask” is still in place after the patterning method and in the final structure.
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Kim discloses in Fig. 1G, where a final structure of a memory element has a hard mask (“first barrier layer 18 serves as a hard mask”, ¶ 0049) is used in the patterning etch steps (see Figs. 1B-1G).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate, “forming a hard mask on the top electrode layer and overlying the lower wire”, where the “hard mask” is still in place after the patterning method and in the final structure, as disclosed by Kim in the system of Jang, for the purpose of simplifying the formation process by utilizing an etch mask film for patterning and subsequent protection during the remainder of the fabrication steps. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 20, the prior art of Jang et al. disclose the method as claim in claim 18, and Jang discloses, wherein forming an auxiliary film includes directly depositing the auxiliary film that includes a nitride of a metal on one of the bottom electrode layer and the resistance switching film (formation of auxiliary film 208b3/308b3, “a sputtering process 242 is performed using the same sputter target 236 to form a metal nitride material layer 308b3 on the metal oxide material layer 308b2. In some embodiments of the invention, the metal nitride material layer 308b1, the metal oxide material layer 308b2 and the metal nitride material layer 308b3 may be formed continuously in the same sputter chamber 226”, ¶ 0048. Where 308b3 is analogous to 208b3, and this element is on bottom electrode layer 208b1/308b1).
Regarding claim 21, the prior art of Jang et al. disclose the method as claimed in claim 18, and Jang discloses, wherein a material of the bottom electrode layer is different from a material of the top electrode layer (212 can have a dopant wherein Fig. 2, there is no dopant in 208b3, ¶ 0030).
Claims 25, 30, 32, 36 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2016/0087199) in view of Lu et al. (US 2022/0310624).
Regarding claim 25, the prior art of Jang discloses in Fig. 2 and 9A (shown below in the rejection of claim 1), a method for manufacturing a semiconductor device (forming a memory device on a semiconductor substrate, ¶ 0008), comprising:
forming a bottom electrode layer (208b1, “the first electrode 208b of the resistive random access memory device 500b is a stacked structure including a metal nitride layer 208b1”, ¶ 0034) over a substrate (“semiconductor substrate 200”, ¶ 0028);
forming a top electrode layer (212, “second electrode 212”, ¶ 0034) over the bottom electrode layer (over 208b1) opposite to the substrate (in position over 208b1 away from 200);
before forming the top electrode layer (212 formed after 210), forming a resistance switching film (210, “resistive switching layer 210”, ¶ 0034);
before forming the top electrode layer (212 formed after 208b3), forming an auxiliary film (208b3, “metal nitride layer 208b3”, ¶ 0034. The term “auxiliary” will be addressed below.); and
performing at least one etch process to form the bottom electrode layer, the auxiliary film, the resistance switching film, and the top electrode layer into a bottom electrode, an auxiliary layer, a switching layer, and a top electrode, respectively (“Referring to FIG. 9A, a lithography process and an etching process is performed to form a hard mask pattern 230 on the second electrode material layer 212a. Then, the hard mask pattern 230 is used as a mask, and an etching process is performed to remove the second electrode material layer 212a, the resistive switching material layer 210a, and the stacked structure composed of the metal nitride material layer 308b1, the metal oxide material layer 308b2 and the metal nitride material layer 308b3 which are not covered by the hard mask pattern 230, so as to form the metal-insulator-metal stacked layer 250b composed of the second electrode 212, the resistive switching layer 210 and first electrode 208b (including the metal nitride layer 208b1, the metal oxide material layer 208b2 and the metal nitride material layer 208b3) as shown in FIG. 2.”, ¶ 0051. It is noted that element 308b1 is analogous to 208b1, 208b3 is analogous to 308b3, 210a is analogous to 210, 212a is analogous to 212. Therefore, this etch patterning step is used to make the resulting structure of Fig. 2.).
Jang does not disclose wherein the metal nitride layer is an “auxiliary film”.
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Lu discloses in Figs. 1 and 2, and ¶ 0051, “With reference to FIG. 1, in some embodiments of this disclosure, the second conductive block 32 can include a conductive auxiliary layer 321 and a conductive plug 322. The conductive auxiliary layer 321 covers the top end of the first conductive block 31, the chamfered structure 311, and the transition wall 312, and covers a sidewall of the contact hole 40. The conductive plug 322 is formed on the conductive auxiliary layer 321 and fills the contact hole 40. The conductive auxiliary layer 321 is configured to block the conductive plug 322 and the first conductive block 31 from interpenetrating.”, and ¶ 0052, “A material of the conductive auxiliary layer 321 can include titanium nitride, etc.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate “an auxiliary layer”, as disclosed by Lu in the system of Jang, for the purpose of providing a barrier metal layer that can prevent migration atoms from of neighboring material layers. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 30, the prior art of Jang et al. disclose the method as claimed in claim 25, wherein forming the auxiliary film includes depositing a metal nitride film on the bottom electrode layer (208b3 on 208b1, where 208b3 has been disclosed as a metal nitride film by Jang, “metal nitride layer 208b3”, ¶ 0034).
Regarding claim 32, the prior art of Jang discloses in Fig. 2 and 9A (shown below in the rejection of claim 1), a method for manufacturing a semiconductor device (forming a memory device on a semiconductor substrate, ¶ 0008), comprising:
forming a bottom electrode layer (208b1, “the first electrode 208b of the resistive random access memory device 500b is a stacked structure including a metal nitride layer 208b1”, ¶ 0034) over a substrate (“semiconductor substrate 200”, ¶ 0028);
forming a top electrode layer (212, “second electrode 212”, ¶ 0034) over the bottom electrode layer (over 208b1) opposite to the substrate (in position over 208b1 away from 200);
forming an auxiliary film (208b3, “metal nitride layer 208b3”, ¶ 0034) between the bottom electrode layer (208b1) and the top electrode layer (212);
forming a resistance switching film (210, “resistive switching layer 210”, ¶ 0034) between the bottom electrode layer (208b1) and the top electrode layer (212);
performing at least one etch process to form the bottom electrode layer, the auxiliary film, the resistance switching film, and the top electrode layer into a bottom electrode, an auxiliary layer, a switching layer, and a top electrode, respectively (“Referring to FIG. 9A, a lithography process and an etching process is performed to form a hard mask pattern 230 on the second electrode material layer 212a. Then, the hard mask pattern 230 is used as a mask, and an etching process is performed to remove the second electrode material layer 212a, the resistive switching material layer 210a, and the stacked structure composed of the metal nitride material layer 308b1, the metal oxide material layer 308b2 and the metal nitride material layer 308b3 which are not covered by the hard mask pattern 230, so as to form the metal-insulator-metal stacked layer 250b composed of the second electrode 212, the resistive switching layer 210 and first electrode 208b (including the metal nitride layer 208b1, the metal oxide material layer 208b2 and the metal nitride material layer 208b3) as shown in FIG. 2.”, ¶ 0051. It is noted that element 308b1 is analogous to 208b1, 208b3 is analogous to 308b3, 210a is analogous to 210, 212a is analogous to 212. Therefore, this etch patterning step is used to make the resulting structure of Fig. 2.).
Jang does not disclose wherein the metal nitride layer is an “auxiliary film”.
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Lu discloses in Figs. 1 and 2, and ¶ 0051, “With reference to FIG. 1, in some embodiments of this disclosure, the second conductive block 32 can include a conductive auxiliary layer 321 and a conductive plug 322. The conductive auxiliary layer 321 covers the top end of the first conductive block 31, the chamfered structure 311, and the transition wall 312, and covers a sidewall of the contact hole 40. The conductive plug 322 is formed on the conductive auxiliary layer 321 and fills the contact hole 40. The conductive auxiliary layer 321 is configured to block the conductive plug 322 and the first conductive block 31 from interpenetrating.”, and ¶ 0052, “A material of the conductive auxiliary layer 321 can include titanium nitride, etc.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate “an auxiliary layer”, as disclosed by Lu in the system of Jang, for the purpose of providing a barrier metal layer that can prevent migration atoms from of neighboring material layers. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 36, the prior art of Jang et al. disclose the method as claimed in claim 32, and Jang discloses, wherein the bottom electrode (208b1) is a more inert electrode than the top electrode (208b1 is shown to be made of metal nitride with a dopant, see ¶ 0029, the dopant being carbon or boron. Then 212 may be made of the same material as 208b1, but without a dopant. Then because the dopant is in place in 208b1 but not 212, then 212 will have more ability to interact with other atoms, since if doped, there is less potential for interaction.), the auxiliary layer (208b31) is disposed between the bottom electrode (208b1) and the switching layer (210).
Regarding claim 37, the prior art of Jang et al. disclose the method as claimed in claim 36, wherein the bottom electrode includes a metal (208b1), and the auxiliary layer (208b3) includes a nitride of the metal (“metal nitride layer 208b3”, ¶ 0034).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2016/0087199) in view of Lu et al. (US 2022/0310624) in view of Kim et al. (US 2014/0287535) in view of Huang et al. (US 10,147,876).
Regarding claim 19, the prior art of Jang et al. disclose the method as claim in claim 18, however, Jang does not specify, “wherein forming an auxiliary film includes performing a nitriding process on a metal to form a nitride of the metal.” It should be noted that Jang’s metal nitride layer 208b1 is formed of titanium nitride (“the metal nitride layer 208b1 and 208b3 may comprise titanium nitride”, ¶ 0034).
Huang discloses in col. 2, lines 60-64, “the first conducting layer may be deposited using a metal-nitride, such as titanium nitride or titanium-aluminum-nitride, in which a nitrogen-argon plasma may be used to sputter and react with a metal target to create the metal-nitride.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate, “wherein forming an auxiliary film includes performing a nitriding process on a metal to form a nitride of the metal”, as disclosed by Huang in the system of Jang, for the purpose of providing the necessary steps required to form a memory electrode layer. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 26, 27, 28 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2016/0087199) in view of Lu et al. (US 2022/0310624) in view of Huang et al. (US 10,147,876).
Regarding claim 26, the prior art of Jang et al. disclose the method as claimed in claim 25, and Jang does not disclose, “wherein forming the auxiliary film includes depositing a metal layer, and performing a nitriding process on the metal layer.”
Huang discloses in col. 2, lines 60-64, “the first conducting layer may be deposited using a metal-nitride, such as titanium nitride or titanium-aluminum-nitride, in which a nitrogen-argon plasma may be used to sputter and react with a metal target to create the metal-nitride.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate, “wherein forming an auxiliary film includes performing a nitriding process on a metal to form a nitride of the metal”, as disclosed by Huang in the system of Jang, for the purpose of providing the necessary steps required to form a memory electrode layer. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 27, the prior art of Jang et al. disclose the method as claimed in claim 26, wherein the auxiliary film (208b3) is formed after forming the bottom electrode layer (after 208b1) and before forming the resistance switching film (before forming 210), an upper portion of the bottom electrode layer serving as the metal layer (totality of 208 where bottom electrode layer 208b1 and nitride layer 208b3).
Regarding claim 28, the prior art of Jang et al. disclose the method as claimed in claim 26, wherein the nitriding process includes gas nitriding in which a nitrogen-rich gas is introduced to contact the metal layer (Huang discloses in col. 2, lines 60-64, “the first conducting layer may be deposited using a metal-nitride, such as titanium nitride or titanium-aluminum-nitride, in which a nitrogen-argon plasma may be used to sputter and react with a metal target to create the metal-nitride.”).
Regarding claim 29, the prior art of Jang et al. disclose the method as claimed in claim 26, wherein the nitriding process includes plasma nitriding in which plasma of a nitrogen carrying gas is generated around the metal layer (Huang discloses in col. 2, lines 60-64, “the first conducting layer may be deposited using a metal-nitride, such as titanium nitride or titanium-aluminum-nitride, in which a nitrogen-argon plasma may be used to sputter and react with a metal target to create the metal-nitride.”).
Claims 22 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2016/0087199) in view of Kim et al. (US 2014/0287535) in view of Lin et al. (US 11,716,915).
Regarding claim 22, the prior art of Jang et al. disclose the method as claimed in claim 21, however Jang does not disclose, “the method further comprising forming a spacer which includes a pair of spacer segments respectively on opposite sidewalls of the top electrode and respectively on opposite sidewalls of the hard mask.”
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Lin discloses in Figs. 12-14, the method further comprising forming a spacer (“sidewall spacer structure 412”, col. 8, lines 44-45) which includes a pair of spacer segments (pair of 412) respectively on opposite sidewalls of the top electrode (on sides of “top electrode 106”, col. 8, line 44) and respectively on opposite sidewalls of the hard mask (on sides of “hard mask 408”, col. 8, line 43).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate, “the method further comprising forming a spacer which includes a pair of spacer segments respectively on opposite sidewalls of the top electrode and respectively on opposite sidewalls of the hard mask”, as disclosed by Lin in the system of Jang, for the purpose of providing support and protection to the sidewalls of the active device layers to ensure proper function after fabrication steps which could damage the side surfaces of the active device layers. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 24, the prior art of Jang et al. disclose the method as claimed in claim 21, and Jang does not disclose, “wherein the pair of spacer segments are respectively on opposite sidewalls of the switching layer, respectively on opposite sidewalls of the auxiliary layer, and respectively on opposite sidewalls of the bottom electrode.”
Lin discloses in Figs. 12-14, wherein the pair of spacer segments (“sidewall spacer structure 412”, col. 8, lines 44-45) are respectively on opposite sidewalls of the switching layer (on sides of “switching layers 110”, col. 17, line 28), respectively on opposite sidewalls of the auxiliary layer (the auxiliary layer has already been disclosed to be between the switching layer and the lower electrode, so by adding sidewall spacers like that of Lin, the auxiliary layer of Jang, would then have sidewall spacers on the auxiliary layer shown by Jang), and respectively on opposite sidewalls of the bottom electrode (on sidewalls of “bottom electrodes 108”, col. 17, line 28).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate, “wherein the pair of spacer segments are respectively on opposite sidewalls of the switching layer, respectively on opposite sidewalls of the auxiliary layer, and respectively on opposite sidewalls of the bottom electrode”, as disclosed by Lin in the system of Jang, for the purpose of providing support and protection to the sidewalls of the active device layers to ensure proper function after fabrication steps which could damage the side surfaces of the active device layers. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2016/0087199) in view of Lu et al. (US 2022/0310624) in view of Lin et al. (US 11,716,915) in view of Peng et al. (US 2019/0165258).
Regarding claim 33, the prior art of Jang et al. disclose the method as claimed in claim 32, and Jang discloses,
wherein the substrate (200) includes a lower interlayer dielectric (ILD) layer (“interlayer dielectric layer 204”, ¶ 0028), a lower wire (“first electrode contact plug 206”, ¶ 0028) formed in the lower ILD layer (206 in 204).
However Jang does not disclose,
“an etch stop layer overlying the lower ILD layer and the lower wire, and a bottom electrode via extending through the etch stop layer to the lower wire.”
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Lin discloses in Fig. 4E, an etch stop layer (“via dielectric layer 416”, col. 9, line 58. The “etch stop” material aspect will be addressed below.) overlying the lower ILD layer (equivalent ILD being 414) and the lower wire (equivalent lower wire being 404b), and a bottom electrode via (108) extending through the etch stop layer (416) to the lower wire (404b).
Peng then shows a similar arrangement with an etch stop (“The etch stop layer 120”, ¶ 0011).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate, “an etch stop layer overlying the lower ILD layer and the lower wire, and a bottom electrode via extending through the etch stop layer to the lower wire”, as disclosed by Lin and Peng in the system of Jang, for the purpose of providing a robust layer that can be patterned so as to serve as a mold for self aligned features. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2016/0087199) in view of Lu et al. (US 2022/0310624) in view of Trinh et al. (US 2019/0165266).
Regarding claim 34, the prior art of Jang et al. disclose the method as claimed in claim 32, however Jang does not disclose,
“wherein a first etch process is performed to form the top electrode layer into the top electrode,
the method further comprising forming a pair of spacer segments respectively on opposite sidewalls of the top electrode, and
performing a second etch process to form the bottom electrode layer, the auxiliary film and the resistance switching film into the bottom electrode, the auxiliary layer, and the switching layer, respectively.”
Trinh discloses in Figs. 1D to 1J, wherein a first etch process is performed to form the top electrode layer into the top electrode (etch from Fig. 1D to 1E, where mask 122 patterns “conductive layer 120”, ¶ 0046),
the method further comprising forming a pair of spacer segments respectively on opposite sidewalls of the top electrode (spacers 126 on sides of 120), and
performing a second etch process (etch from Fig. 1G to 1H) to form the bottom electrode layer (“conductive layer 112”, ¶ 0048), the auxiliary film (already disclosed between the switching film and lower electrode, which would be in place in the combination with Trinh) and the resistance switching film (equivalent film being 114) into the bottom electrode, the auxiliary layer, and the switching layer, respectively (as shown in Fig. 1H).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate, “wherein a first etch process is performed to form the top electrode layer into the top electrode,
the method further comprising forming a pair of spacer segments respectively on opposite sidewalls of the top electrode, and
performing a second etch process to form the bottom electrode layer, the auxiliary film and the resistance switching film into the bottom electrode, the auxiliary layer, and the switching layer, respectively”, as disclosed by Trinh and Peng in the system of Jang, for the purpose of protecting the upper layers of the stack which are more vulnerable to damage during the patterning etch. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 35, the prior art of Jang et al. disclose the method as claimed in claim 34, and Trinh shows, wherein forming the pair of spacer segments (126) includes forming a spacer layer over the top electrode and the resistance switching film (124 in Fig. 1F, where 124 is over 120 and part of 114), and performing an additional etch process to etch (“FIG. 1G, the protective layer 124 is partially removed to form a protective element 126, in accordance with some embodiments. The protective element 126 covers sidewalls of the conductive layer 120, the capping layer 118, and the ion diffusion barrier layer 116. An etching process may be used to form the protective element 126. During the etching process, the mask element 122 may also be etched. As a result, a mask element 122′ with a smaller thickness may be formed.”, ¶ 0046) the spacer layer into the pair of spacer segments (pair of 126).
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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