DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 17-36 in the reply filed on 3/31/2026 is acknowledged.
Claims 1-16 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected embodiment, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/31/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-24, 26, and 29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al (U.S. Pub #2022/0029023).
With respect to claim 21, Chen teaches a method, comprising:
forming an active region over a substrate (Fig. 3, 202) and extending lengthwise along a first direction (Fig. 3, X), the active region comprising a channel region (Fig. 3, 10) and a source/drain region (Fig. 3, 20);
forming an isolation feature adjacent to the active region (Paragraph 15: “The substrate 202 may have isolation features interposing the regions providing different device types.”);
forming a gate stack (Fig. 3, 210 and Paragraph 22) over the channel region and the isolation feature and extending lengthwise along a second direction (Fig. 3, Y) different from the first direction;
recessing the active region to form a source/drain trench (Fig. 3, 228) extending through the source/drain region;
forming a dielectric layer (Fig. 4, 230 and Paragraph 29) in the source/drain trench and extending along a sidewall surface of a lower portion (Fig. 3, i.e. lower layer 208) of the channel region;
epitaxially growing a semiconductor layer (Fig. 6, 234 and Paragraph 31) in the source/drain trench, wherein the semiconductor layer is spaced apart from the lower portion of the channel region (Fig. 6, i.e. lower layer 208) by the dielectric layer (Fig. 6, 224) along the first direction; and
forming a source/drain feature (Fig. 13, 242 and Paragraph 38) laterally adjacent to an upper portion of the channel region (Fig. 13, i.e. upper layer 208), wherein the source/drain feature is disposed over the semiconductor layer and the dielectric layer.
With respect to claim 22, Chen teaches the channel region comprises a plurality of nanostructures (Fig. 3, 208) interleaved by a plurality of sacrificial layers (Fig. 3, 206 and Paragraph 25), and the method further comprises:
selectively removing the gate stack (Paragraph 45);
selectively removing the plurality of sacrificial layers (Paragraph 46); and
forming a gate structure (Fig. 19, 254 and Paragraph 43) wrapping around at least one of the plurality of nanostructures.
With respect to claim 23, Chen teaches that the dielectric layer (Fig. 4, 224) extends along a sidewall surface of a bottommost nanostructure (Fig. 4, 208) of the plurality of nanostructures.
With respect to claim 24, Chen teaches
forming inner spacer features (Fig. 5, 224) adjacent to the plurality of sacrificial layers, wherein a top surface of the dielectric layer (Fig. 5, 230) is above a top surface of a bottommost one of the inner spacer features.
With respect to claim 26, Chen teaches that the source/drain feature comprises a p-type dopant (Paragraph 38), and the source/drain feature (Fig. 13, 242) extends on a top surface of the semiconductor layer (Fig. 13, 2340).
With respect to claim 29, Chen teaches that the semiconductor layer is substantially undoped (Paragraph 31-34).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 30-32, 34, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (U.S. Pub #2022/0029023), in view of Xie et al (U.S. Pub #2022/0406664).
With respect to claim 30, Chen teaches a method, comprising:
forming a first active region (Fig. 3, A) and a second active region (Fig. 3, B) over a substrate (Fig. 3, 202);
forming an isolation feature (Paragraph 15: “The substrate 202 may have isolation features interposing the regions providing different device types.” ) between the first active region and the second active region;
forming a first trench and a second trench (Fig. 3, 228) extending through the first active region and the second active region, respectively;
selectively growing a first source/drain feature (Fig. 13, 242 and Paragraph 38) in the first trench,
after the selectively growing of the first source/drain feature, depositing a dielectric layer (Fig. 7, 246), wherein the dielectric layer comprises a first portion on the first source/drain feature and a second portion in the second trench (Paragraph 40, the dielectric layer 246 is blanket deposited); and
after the depositing of the dielectric layer, epitaxially growing a second source/drain feature (Fig. 17, 248 and Paragraph 41) in the second trench and over the second portion of the dielectric layer,
wherein the first source/drain feature and the second source/drain feature comprise dopants of different doping polarities (Paragraph 38 and 41, p-type and n-type respectively).
Chen does not teach
wherein the first source/drain feature overhangs the isolation feature;
Xie teaches a structure wherein a source/drain feature (Fig. 3, 124 or 128; Paragraph 36-37) overhangs an isolation feature (Fig. 3, 118 and Paragraph 29).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the source/drain feature of Chen to overhang the isolation feature as taught by Xie in order to achieve the predictable result of epitaxially forming the S/D feature (Paragraph 36-37, wherein the shape is a result of the epitaxial process) and to allow a metal contact to the S/D region to transfer desirable stress to the structure (Paragraph 55).
With respect to claim 31, Chen teaches that the first source/drain feature is a p-type doped source/drain feature (Paragraph 38), and the second source/drain feature is an n-type doped source/drain feature (Paragraph 41).
With respect to claim 32, Chen teaches
before the selectively growing of the first source/drain feature, forming a first insulation layer (Fig. 10, 238) in the first trench and a second insulation layer (Fig. 11, 240) in the second trench; and
forming a first semiconductor layer (Fig. 10, 2340) in the first trench and laterally adjacent to the first insulation layer and a second semiconductor layer (Fig. 11, 2350) in the second trench and laterally adjacent to the second insulation layer.
With respect to claim 34, Chen teaches that the first active region (Fig. 3, A) comprises a first channel region including a first plurality of nanostructures (Fig. 3, 204), the second active region (Fig. 3, B) comprises a second channel region including a second plurality of nanostructures (Fig. 3, 204).
With respect to claim 35, Chen teaches that the first insulation layer (Fig. 5, 230) covers a sidewall surface of a bottommost one of the first plurality of nanostructures (Fig. 5, bottom 208 in region A), and the second insulation layer (Fig. 5, 230) covers a sidewall surface of a bottommost one of the second plurality of nanostructures (Fig. 5, bottom 208 in region B).
Allowable Subject Matter
Claim 25, 27, 28, 33, and 36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance: the best prior art of record does not teach or fairly suggest, along with the other limitations
in claim 17:
forming a first semiconductor layer in a bottom portion of the first source/drain opening;
forming a first dielectric layer extending along a sidewall surface of a middle portion of the first source/drain opening and on the first semiconductor layer, wherein an entirety of a sidewall surface of a bottommost channel layer of the plurality of channel layers is covered by the first dielectric layer;
forming a second semiconductor layer on the first semiconductor layer, wherein a sidewall surface of the second semiconductor layer is in direct contact with the first dielectric layer;
forming a first source/drain feature on the second semiconductor layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN P SANDVIK/Primary Examiner, Art Unit 2812
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