CTNF 18/404,233 CTNF 79655 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Invention I, Species 1 and Subspecies B, in the reply filed on May 18, 2026 is acknowledged. Claims 6, 9 and 17-20 have been cancelled and new claims 21-26 have been added. Therefore, claims 1-5, 7-8, 10-16 and 21-26 are ready for examination. Specification 07-29 AIA The disclosure is objected to because of the following informalities: in paragraph [0030] of the specification “isolation structure 110” should read “isolation structure 126” . Appropriate correction is required. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-2, 4, 10-11 and 21 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lin et al. (US 2023/0123484, hereinafter “Lin”) . Regarding claim 1, Lin teaches in Fig. 2H (shown below) and related text a semiconductor device, comprising: a substrate (102, Fig. 2H and ¶[0018]) ; first and second nanostructured channel regions (106, Fig. 2H and ¶[0019]) disposed on the substrate; a gate structure (140, Fig. 2H and ¶[0055]) surrounding the first and second nanostructured channel regions (Fig. 2H) ; an inner gate spacer (126, Fig. 2H and ¶[0033]) disposed along a sidewall of the gate structure and between the first and second nanostructured channel regions (Fig. 2H) ; a source/drain (S/D) region (132, 134, 138, Fig. 2H and ¶¶[0036]-[0045]) , comprising: an epitaxial liner (132, 134, Fig. 2H and ¶¶[0036]-[0040]) disposed along sidewalls of the first and second nanostructured channel regions and the inner gate spacer (Fig. 2H) ; and a germanium-based epitaxial region (138, Fig. 2H and ¶[0046]) disposed on the epitaxial liner; and an isolation structure (130, Fig. 2H and ¶[0035]) disposed between the germanium-based epitaxial region (138, Fig. 2H) and the substrate (102, Fig. 2H) . PNG media_image1.png 853 616 media_image1.png Greyscale Regarding claim 2 (1), Lin teaches wherein the epitaxial liner comprises: a first portion (132, 134, Fig. 2H) with a first thickness disposed on the sidewalls of the first and second nanostructured channel regions (106, Fig. 2H) ; and a second portion (132, 134, Fig. 2H) with a second thickness disposed on the sidewalls of the inner gate spacer (126, Fig. 2H) , wherein the first thickness is greater than the second thickness (Fig. 2H) . Regarding claim 4 (1), Lin teaches wherein the epitaxial liner comprises a doped germanium-free silicon layer (¶¶[0039]-[0042]) . Regarding claim 10 (1), Lin teaches wherein the isolation structure comprises an undoped semiconductor layer (¶[0035]) . Regarding claim 11, Lin teaches in Fig. 2H (shown above) and related text semiconductor device, comprising: a substrate (102, Fig. 2H and ¶[0018]) ; first and second nanosheet layers (106, Fig. 2H and ¶[0019]) disposed on the substrate (102, Fig. 2H) ; first and second gate structures (140, Fig. 2H and ¶[0055]) surrounding the first and second nanosheet layers, respectively (Fig. 2H) ; first and second gate spacers (126, Fig. 2H and ¶[0033]) disposed along sidewalls of the first and second gate structures (140, Fig. 2H) , respectively; and a source/drain (S/D) (132, 134, 138, Fig. 2H and ¶¶[0036]-[0045]) , comprising: a first epitaxial liner (132, 134 on the left side of the device, Fig. 2H and ¶¶[0036]-[0040]) disposed as a continuous layer along sidewalls of the first nanosheet layer and the first gate spacer (e.g. on the left side of the device, Fig. 2H) ; a second epitaxial liner (132, 134 on the right side of the device, Fig. 2H and ¶¶[0036]-[0040]) disposed as a continuous layer along sidewalls of the second nanosheet layer and the second gate spacer (e.g. on the right side of the device, Fig. 2H) ; and an epitaxial region (138, Fig. 2H and ¶[0046]) disposed between the first and second epitaxial liners. Regarding claim 21, Lai teaches in Fig. 22A (shown below) and related text a semiconductor device, comprising: a substrate (102, Fig. 2H and ¶[0018]) ; a first stack of nanosheet layers (106, Fig. 2H and ¶[0019]) disposed on the substrate (102, Fig. 2H) ; a second stack of nanosheet layers (106, Fig. 2H and ¶[0019]) disposed on the substrate (102, Fig. 2H) ; an isolation structure (130, Fig. 2H and ¶[0035]) extending between sidewalls of nanosheet layers in the first and second stacks of nanosheet layers (i.e. 130 extends between the sidewalls of nanosheet layers in a similar manner that an isolation structure 126 disclosed by the Applicant extends between sidewalls of nanosheet layer 110) ; first and second gate structures (140, Fig. 2H and ¶[0055]) disposed on the first and second stacks of nanosheet layers (Fig. 2H) , respectively; first and second gate spacers (126, Fig. 2H and ¶[0033]) disposed along sidewalls of the first and second gate structures (140, Fig. 2H) , respectively; and a source/drain (S/D) region (132, 134, 138, Fig. 2H and ¶¶[0036]-[0045]) , comprising: a first epitaxial liner (e.g. 132, 134 on the left side, Fig. 2H and ¶¶[0036]-[0040]) disposed as a continuous layer along sidewalls of the first gate spacers and sidewalls of the first stack of nanosheet layers; a second epitaxial liner (e.g. 132, 134 on the right side, Fig. 2H) disposed as a continuous layer along sidewalls of the second gate spacers and sidewalls of second stack of nanosheet layers, and, an epitaxial region (138, Fig. 2H and ¶[0046]) disposed between the first and second epitaxial liners . 07-15-03-aia AIA Claim(s) 1-2, 4, 11-12 and 14-15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 2023/0402535, hereinafter “Kim”) . Regarding claim 1, Kim teaches in Figs. 9C and 20 (Fig. 20 shown below) and related text a semiconductor device, comprising: a substrate (100, Fig. 20 and ¶[0022]) ; first and second nanostructured channel regions (SP1-SP3, Fig. 20 and ¶[0039]) disposed on the substrate; a gate structure (GE, Fig. 20 and ¶[0046]) surrounding the first and second nanostructured channel regions (Fig. 20) ; an inner gate spacer (ISP, Fig. 20 and ¶[0048]) disposed along a sidewall of the gate structure and between the first and second nanostructured channel regions (Fig. 20) ; a source/drain (S/D) region (SD1 or SD2, Fig. 20 and ¶¶[0040]-[0044] and [0093]) , comprising: an epitaxial liner (BFL, Fig. 20 and ¶¶[0042] and [0093]) disposed along sidewalls of the first and second nanostructured channel regions and the inner gate spacer (Fig. 20) ; and a germanium-based epitaxial region (MIL, Fig. 20 and ¶¶[0042] and [0034]) disposed on the epitaxial liner; and an isolation structure (ST, Fig. 9C and ¶[0037]) disposed between the germanium-based epitaxial region (i.e. SD1, Fig. 9C) and the substrate (100, AP1, Fig. 9C) . PNG media_image2.png 853 685 media_image2.png Greyscale Regarding claim 2 (1), Kim teaches wherein the epitaxial liner comprises: a first portion (i.e. portion of BFL on SP1-SP3, Fig. 20) with a first thickness disposed on the sidewalls of the first and second nanostructured channel regions (SP1-SP3, Fig. 20) ; and a second portion with a second thickness disposed on the sidewalls of the inner gate spacer (ISP, Fig. 20) , wherein the first thickness is greater than the second thickness (Fig. 20) . Regarding claim 4 (1), Kim teaches wherein the epitaxial liner comprises a doped germanium-free silicon layer (i.e. Kim teaches that the liner might be made of silicon, germanium and silicon-germanium, (¶¶[0034] and [0043]), which can be doped with arsenic (As) (¶[0095])) . Regarding claim 11, Kim teaches in Figs. 9C and 20 (Fig. 20 shown above) and related text semiconductor device, comprising: a substrate (100, AP1, AP2, Fig. 20 and ¶[0022]) ; first and second nanosheet layers (SP1-SP3, Fig. 20 and ¶[0039]) disposed on the substrate (100, Fig. 20) ; first and second gate structures (GE, Fig. 20 and ¶[0046]) surrounding the first and second nanosheet layers, respectively (Fig. 20) ; first and second gate spacers (e.g. ISPs located on both sides of MIL, Fig. 20) disposed along sidewalls of the first and second gate structures (e.g. gate structures disposed on the left and right of the device, Fig. 20) , respectively; and a source/drain (S/D) region (SD1 or SD2, Fig. 20 and ¶¶[0040]-[0044] and [0093]) , comprising: a first epitaxial liner (BFL, Fig. 20 and ¶¶[0042] and [0093]) disposed as a continuous layer along sidewalls of the first nanosheet layer and the first gate spacer (e.g. on the left side of the device, Fig. 20) ; a second epitaxial liner disposed as a continuous layer along sidewalls of the second nanosheet layer and the second gate spacer (e.g. on the right side of the device, Fig. 20) ; and an epitaxial region (MIL, Fig. 20, ¶¶[0042] and [0034]) disposed between the first and second epitaxial liners. Regarding claim 12 (11), Kim teaches wherein the first and second epitaxial liners comprises first and second germanium-free epitaxial liners, respectively (i.e. Kim teaches that the liner BFL on both sides of the device might be made of silicon, germanium and silicon-germanium, (¶¶[0034] and [0043]), which can be doped with arsenic (As) (¶[0095])) . Regarding claim 14 (11), Kim teaches wherein the first and second epitaxial liners comprise doped germanium-free silicon layers (i.e. Kim teaches that the liner might be made of silicon, germanium and silicon-germanium, (¶¶[0034] and [0043]), which can be doped with arsenic (As) (¶[0095])) . Regarding claim 15 (11), Kim teaches wherein the first and second epitaxial liners comprise boron-doped or gallium-doped silicon layers (i.e. Kim teaches that liner BFL might be made of silicon, germanium and silicon-germanium, ¶[0133]) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 3, 8 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over as Lin or Kim applied to claim 1 and 21 above, respectively, and further in view of Liu et al. (US 2022/0367625, hereinafter “Liu”, cited on IDS) . Regarding claim 3 (1), teaching of Lin was discussed above in the rejection of claim 1 and includes wherein the epitaxial liner comprises a first portion with a faceted sidewall profile disposed on the sidewalls of the first and second nanostructured channel regions (Fig. 2H) . Lin, however, does not explicitly teach that a second portion disposed on the sidewalls of the inner gate spacer has a curved sidewall profile. Liu, in a similar field of endeavor, teaches in Figs. 18A-18E that epitaxial liner, similar to that disclosed by Lin, can have different profiles, including a curved sidewall profile (e.g. Fig. 18E) depending on the surface on which the spacer is grown and growth conditions used (¶[0073]) in order to meet specific design requirements for the device. Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results and, as such, it would have been obvious to grow the second portion of the epitaxial liner disclosed by Lin so that it has a curved sidewall profile as disclosed by Liu, in order to meet specific design requirements for the device. Regarding claim 8 (1), teaching of Kim was discussed above in the rejection of claim 1 and includes wherein the epitaxial liner comprises a faceted sidewall (Fig. 20) . Kim, however, does not explicitly teach with a crystal orientation that is same as a crystal orientation of the substrate. Liu in a similar field of endeavor teaches in Figs. 18A-18E and related text, that the faceted sidewall with a crystal orientation can be the same as a crystal orientation of the substrate (¶[0073]). Thus, since the prior art teaches all of the claim elements using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the epitaxial liner disclosed by Kim with a crystal orientation that is same as a crystal orientation of the substrate, as disclosed by Liu in order to meet specific design characteristics for the device. Regarding claim 25 (21), teaching of Lin was discussed above in the rejection of claim 21 and includes wherein each of the first and second epitaxial liners comprises a first portion with a faceted sidewall profile (Fig. 2H) . Lin, however, does not explicitly teach that a second portion has a curved sidewall profile. Liu, in a similar field of endeavor, teaches in Figs. 18A-18E that epitaxial liner, similar to that disclosed by Lin, can have different profiles, including a curved sidewall profile (e.g. Fig. 18E) depending on the surface on which the spacer is grown and growth conditions used (¶[0073]) in order to meet specific design requirements for the device. Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results and, as such, it would have been obvious to grow the second portion of the first and second epitaxial liners disclosed by Lin so that it they have a curved sidewall profile, as disclosed by Liu, in order to meet specific design requirements for the device . 07-21-aia AIA Claim (s) 5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin or Kim applied to claim 1, above, and further in view of Lin et al. (US 2023/0063612, hereinafter “Lin `612”) . Regarding claim 5 (1), teaching of Lin or Kim was discussed above in the rejection of claim 1 and includes wherein the p-type epitaxial liner comprises SiGe material and a boron and gallium dopants (Lin, ¶¶[0038] and Kim, ¶¶[0034], [0043] and [0133]) . While Lin or Kim do not explicitly teach that the p-type epitaxial liner with boron or gallium dopants is a germanium-free silicon layer, substituting Si (i.e. germanium-free silicon) for SiGe disclosed by Lin or Kim would be within capabilities of one of ordinary skill in the art as the two materials were art recognized equivalents before the effective filing date of the invention as evidenced by Lin `612 (¶[0063]) . Therefore, because these two materials were art-recognized equivalents before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to substitute Si (germanium-fee silicon) for SiGe for the liner material. Regarding claim 7 (1), teaching of Lin was discussed above in the rejection of claim 1 and includes wherein the epitaxial liner comprises a silicon layer comprising boron or gallium atoms with concentration of 2x10 20 atoms/cm 3 to about 7x10 20 atoms/cm 3 (¶[0038]) . While Lin does not explicitly teach that the p-type epitaxial liner with boron or gallium dopants is a germanium-free silicon layer, substituting Si (i.e. germanium-free silicon) for SiGe disclosed by Lin would be within capabilities of one of ordinary skill in the art as the two materials were art recognized equivalents before the effective filing date of the invention as evidenced by Lin `612 (¶[0063]) . Therefore, because these two materials were art-recognized equivalents before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to substitute Si (germanium-fee silicon) for SiGe for the liner material . 07-21-aia AIA Claim (s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over as Lin applied to claim 11, respectively, and further in view of Cheng et al. (US 2020/0044060, hereinafter “Cheng”) . Regarding claim 16 (11), teaching of Lin was discussed above in the rejection of claim 11. Lin, however, does not explicitly teach wherein a width of the first epitaxial liner is greater than a width of the first nanosheet layer. Nonetheless, forming the epitaxial liner disclosed by Lin so that the is greater than a width of the first nanosheet layer would be obvious to one of ordinary skill in the art before the effective filing date of the filed invention as evidenced by Cheng (Figs. 26A-26B and 27A-27B and ¶[0102]) in order to fully cover the nanosheet layer and promote adhesion to the nanosheet layer of the subsequently deposited epitaxial region. Thus, since the prior art teaches all of the claim element, using such elements would lead to predictable results and, as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the epitaxial liner disclosed by Lin so that the is greater than a width of the first nanosheet layer as disclosed by Cheng, in order to fully cover the nanosheet layer and promote adhesion to the nanosheet layer of the subsequently deposited epitaxial region 07-21-aia AIA Claim (s) 21-24 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 2022/0122893, hereinafter “Lai”) in view of Liu et al (US 2022/0367625, hereinafter “Liu”, cited on June 2, 2026 IDS) . Regarding claim 21, Lai teaches in Fig. 22A (shown below) and related text a semiconductor device, comprising: a substrate (202, Fig. 22A and ¶[0014]) ; a first stack of nanosheet layers (e.g. 216 on the left side, Fig. 22A and ¶[0015]) disposed on the substrate (202, Fig. 22A) ; a second stack of nanosheet layers (e.g. 216 on the right side, Fig. 22A and ¶[0015]) disposed on the substrate; an isolation structure (e.g. 240, Fig. 22A and ¶[0027]) extending between sidewalls of nanosheet layers in the first and second stacks of nanosheet layers (i.e. 240 extends between the sidewalls of nanosheet layers in a similar manner that an isolation structure 126 disclosed by the Applicant extends between sidewalls of nanosheet layer 110) ; first and second gate structures (e.g. 216 on the left side, Fig. 22A and ¶[0015]) disposed on the first and second stacks of nanosheet layers (Fig. 22A) , respectively; first and second gate spacers (240’, Fig. 22A and ¶[0038]) disposed along sidewalls of the first and second gate structures (268, Fig. 22A and ¶[0038]) , respectively; and a source/drain (S/D) region (254, Fig. 22A and ¶[0031]) , comprising: an epitaxial region (254, Fig. 22A and ¶[0031]) . PNG media_image3.png 519 399 media_image3.png Greyscale Lai, however, does not explicitly teach a first epitaxial liner disposed as a continuous layer along sidewalls of the first gate spacers and sidewalls of the first stack of nanosheet layers and a second epitaxial liner disposed as a continuous layer along sidewalls of the second gate spacers and sidewalls of second stack of nanosheet layers, and, as a result, that the epitaxial region is disposed between the first and second epitaxial liners. Liu, in a similar field of endeavor, teaches that source/drain regions (98, Fig. 26 and ¶[0060]) similar to those disclosed by Lai can include multiple semiconductor layers including epitaxial liner layers (98A, Fig. 26 and ¶[0060]) in order to improve adhesion of the source/drain material to the source/drain recess (¶[0060]) . Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the epitaxial liner as disclosed by Liu in the device disclosed by Lai in order to improve adhesion of the source/drain material to the source/drain recess. It is noted that when the epitaxial liner disclosed by Liu is formed in the device disclosed by Lai the epitaxial region disclosed by Lai would be disposed between the first and second epitaxial liners. Regarding claim 22 (21), the combined teaching of Lai and Liu discloses wherein the first and second epitaxial liners comprise doped germanium-free silicon layers (Lai, ¶¶[0036]-[0037], [0056] and [0058]) . Regarding claim 23 (21), the combined teaching of Lai and Liu discloses wherein the first and second epitaxial liners comprise boron-doped or gallium-doped germanium-free silicon layers (Lai, ¶¶[0037], [0056] and [0058]) . Regarding claim 24 (21), the combined teaching of Lai and Liu discloses wherein the first epitaxial liner comprises: a first portion (Liu, i.e. portion of 98A on 68, Figs. 19A, 26 and ¶[0073]) with a first thickness on the sidewalls of the first stack of nanosheet layers (Liu, 68, Figs. 19A, 26 and ¶[0040]) ; and a second portion (Liu, i.e. portion of 98A on 96, Figs. 19A, 19C, 26 and ¶[0073]) with a second thickness on the sidewalls of the first gate spacers (Liu, 96, Figs. 19A, 19C, 26 and ¶[0049]) , wherein the first thickness is greater than the second thickness (Liu, Figs. 19A, 19C and 26) . Regarding claim 26 (21), the combined teaching of Lai and Liu discloses wherein each of the first and second epitaxial liners comprises a faceted sidewall (Liu, Figs. 19A-19E) with a crystal orientation that is same as a crystal orientation of the substrate (Liu, ¶[0073]) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim (s) 13 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: Regarding claim 13, the prior art of record, alone or in combination, and to the examiner’s knowledge does not teach, disclose, suggest, or render obvious, at least to the skilled artisan, the instant invention regarding a semiconductor device, particularly characterized by an undoped semiconductor layer disposed on the substrate and between the first and second nanosheet layers, wherein the first and second epitaxial liners and the epitaxial region are disposed on and in contact with the undoped semiconductor layer, in combination with all other elements of the semiconductor device recited in the claim(s). The closest prior art of record to Kim et al. (US 2023/0402535), Lin et al. (US 2023/0123484) or Lai et al. (US 2022/0122893) and Liu (US 2022/0367625) fail to teach the above noted elements of the claim. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANETA B CIESLEWICZ whose telephone number is 303-297-4232. The examiner can normally be reached M-F 8:30 AM - 2:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.B.C/Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893 Application/Control Number: 18/404,233 Page 2 Art Unit: 2893 Application/Control Number: 18/404,233 Page 3 Art Unit: 2893 Application/Control Number: 18/404,233 Page 4 Art Unit: 2893 Application/Control Number: 18/404,233 Page 5 Art Unit: 2893 Application/Control Number: 18/404,233 Page 6 Art Unit: 2893 Application/Control Number: 18/404,233 Page 7 Art Unit: 2893 Application/Control Number: 18/404,233 Page 8 Art Unit: 2893 Application/Control Number: 18/404,233 Page 9 Art Unit: 2893 Application/Control Number: 18/404,233 Page 10 Art Unit: 2893 Application/Control Number: 18/404,233 Page 11 Art Unit: 2893 Application/Control Number: 18/404,233 Page 12 Art Unit: 2893 Application/Control Number: 18/404,233 Page 14 Art Unit: 2893 Application/Control Number: 18/404,233 Page 15 Art Unit: 2893 Application/Control Number: 18/404,233 Page 16 Art Unit: 2893 Application/Control Number: 18/404,233 Page 17 Art Unit: 2893
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