Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang, US 2022/0262695 (listed in the IDS dated 12-9-2024).
Regarding Claim 1, Chang discloses a package (12C; Figs. 4C, 10F; ¶ 0090 “semiconductor package 12C”) comprising:
a first die (200; Fig. 10C; ¶ 0090 “die 200”) over (Fig. 4C, 10F) and bonded to (¶ 0090 “die 200 may be bonded to…die 100”) a first side (Fig. 4C¶ 0090 “in a face-to-back configuration”) of a second die (100; Fig. 4C; ¶ 0090 “die 100”), wherein the second die (100) comprises:
a first substrate (102; Figs. 4C, 10F; ¶ 0093 “semiconductor substrate 102”);
a first interconnect structure (104; Figs. 4C, 10F; ¶ 0076 “structure 104”) over the first substrate (Figs. 4C, 10F);
a seal ring (410M; Figs. 4C, 10F; ¶ 0093 “seal ring 410M”) disposed within the first interconnect structure (Figs. 4C, 10F);
first dummy through substrate vias (TSVs) (410SD; Figs. 4C, 10F; ¶ 0093 “substrate-dielectric…410SD”) extending through (Figs. 4C, 10F; ¶ 0093 “410SD that extends through the…semiconductor substrate 102”) edge regions (Figs. 4C, 10F; ¶ 0092 “410 may be disposed inside the perimeter of the…die 100”) of the first substrate (Figs. 4C, 10F; ¶ 0093 “410SD that extends through the…semiconductor substrate 102”) of the second die (100) and in physical contact with the seal ring (Figs. 4C, 10F; ¶ 0093 “410SD, and the metal features seal ring 410M may directly contact one another”); and
functional TSVs (162; Figs. 4C, 10F; ¶ 0094 “TSV structures 162”; ¶ 0035 “162 may be electrically connected to the first metal interconnect structure 110”) extending through a central region (Figs. 4C, 10F) of the first substrate (Figs. 4C, 10F; ¶ 0035 “162 that extends though the first semiconductor substrate 102”) of the second die (100).
Regarding Claim 2, Chang discloses
wherein the second die (100) further comprises metallization patterns (106; Figs. 4C, 10F; ¶ 0033 “metal features 106 may be any of a variety of metal via structures and metal lines”) disposed in the first interconnect structure (Figs. 4C, 10F; ¶ 0033 “metal features 106 disposed in the…structure 104”),
wherein the seal ring (410M) surrounds the metallization patterns (Figs. 4C, 10F), and
wherein the first dummy TSVs (410SD) and the functional TSVs (162) extend partially through (Figs. 4C, 10F) the first interconnect structure (104).
Regarding Claim 3, Chang discloses
wherein the first dummy TSVs (410SD) are disposed around (Figs. 4C, 10F; ¶ 0092, 0153) the functional TSVs (162), and
wherein the first dummy TSVs (410SD) are disposed under and are overlapped by (Figs. 4C, 10F; ¶ 0093 “410SD, and the metal features seal ring 410M may directly contact one another and may overlap in the lateral direction L”) the seal ring (410M).
Regarding Claim 4, Chang discloses
conductive connectors (108; Fig. 4C; ¶ 0093 “bonding pads 108”) on a second side (Fig. 4C side closest to layer 312) of the second die (100), the conductive connectors being electrically coupled to (Fig. 4C; ¶ 0034 “metal features 106 may be electrically connected to bonding pads 108”) the functional TSVs (162) and the metallization patterns (106).
Claims 21 and 23-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (Wang”), US 2022/0254737.
Regarding Claim 21, Wang discloses a package (30; Figs. 2C, 3A; ¶ 0032) comprising:
a first die (100; Figs. 2C, 3A; ¶ 0014 “100 includes…a semiconductor substrate and a plurality of active or passive devices formed on…the semiconductor substrate”) comprising:
a first substrate (not labeled; Figs. 2C, 3A; ¶ 0014 “100 includes a…semiconductor substrate”);
a first interconnect structure (300, 700; Fig. 3A; ¶ 0019 “interconnection layer 300”, ¶ 0023 “interconnection layer 700,”) over the first substrate (Fig. 3A), the first interconnect structure comprising metallization patterns (¶ 0019 “interconnection layer 300 is formed by…metallization layers”; ¶ 0023 “interconnection layer 700 is formed by…metallization layers”);
a seal ring (302b, 702b; Figs. 2C, 3A; ¶ 0032 “seal ring structure 702b”;¶ 0033 “seal ring structure 302b”) disposed within the first interconnect structure (¶ 0019 “interconnection layer 300 includes a first seal ring structure 302 located in the peripheral region PR closely adjacent to the scribe line 102”; ¶ 0023 “interconnection layer 700 includes a second seal ring structure 702 located in the peripheral region PR closely adjacent to the scribe line 102”) and surrounding the metallization patterns (¶ 0019 “Other portions of the first interconnection layer 300 may include interconnect structures not shown for other routing requirements of the devices formed in the active region AR of the semiconductor device 100”, ¶ 0023 “Other portions of the second interconnection layer 700 may include interconnect structures not shown for other routing requirements of the devices formed in the active region AR of the semiconductor device 100” therefore the seal ring 302b, 702b surrounds metallization patterns in the active region AR);
first dummy through substrate vias (TSVs) (200b, 204b; Figs. 2C, 3A; ¶ 0018 “TSVs 200 located in the peripheral region PR may be electrically floating”; ¶ 0020 “seal ring 306 is electrically floated”; ¶ 0024 “seal ring 706 is electrically floated” therefore the TSVs 200b, 204b are dummy TSVs) extending through edge regions (Figs. 2C, 3A; ¶ 0018 “TSVs 200 located in the peripheral region PR”) of the first substrate of the first die (Figs. 2C, 3A) and in physical contact with the seal ring (Figs. 2C, 3A; ¶ 0033 “TSVs 200b physically connect the second seal ring loop pattern 306b of the first seal ring 306 and the second seal ring loop pattern 706b of the second seal ring 706”); and
second dummy TSVs (200a, 204a; Figs. 2C, 3A; ¶ 0018 “TSVs 200 located in the peripheral region PR may be electrically floating”; ¶ 0020 “seal ring 306 is electrically floated”; ¶ 0024 “seal ring 706 is electrically floated” therefore the TSVs 200a, 204a are dummy TSVs) that extend through the edge regions (Figs. 2C, 3A; ¶ 0018 “TSVs 200 located in the peripheral region PR”) of the first die (Figs. 2C, 3A), wherein the second dummy TSVs (200a, 204a) are not in physical contact (Figs. 2C, 3A; ¶ 0033 “second seal ring loop pattern 306b surrounding the first seal ring loop pattern 306a” and “first TSVs 200a are completely covered/shielded by the first seal ring loop patterns 306a, 706a and the second TSVs 200b are completely covered/shielded by the second seal ring loop patterns 306b, 706b”; ¶ 0032 “second seal ring loop pattern 706b surrounding the first seal ring loop pattern 706a” and “first TSVs 200a and these second TSVs 200b are not overlapped with each other” therefore the second dummy TSVs 200a, 204a are not in physical contact with the seal ring 302b, 702b) with the seal ring (302b, 702b).
Regarding Claim 23. Wang discloses further comprising functional TSVs (¶ 0018 “a plurality of TSVs (not shown) may be formed in the active region AR” and “the TSVs formed in the active region AR are configured to transmit signals between the front side and the backside of the semiconductor device 100, so these TSVs are electrically connected to the active devices or the passive devices located in the active region AR” therefore the TSVs in the active region AR are functional TSVs) extending through a central region (Fig. 3A; ¶ 0018 “a plurality of TSVs (not shown) may be formed in the active region AR”; ¶ 0014 “the peripheral region PR surrounds the active region AR”) of the first substrate of the first die (100).
Regarding Claim 24, Wang discloses wherein the second dummy TSVs (200a, 204a) are disposed adjacent to corner regions (Fig. 2C; ¶ 0033 “first TSVs 200a and the second TSVs 200b are arranged in a staggered manner”) of the seal ring (302b, 702b).
Regarding Claim 25, Wang discloses wherein in a top-down view (Fig. 2C; ¶ 0006), the second dummy TSVs (200a, 204a) are disposed within an inner perimeter (Figs. 2C, 3A; ¶ 0033 “TSVs 200a physically connect the first seal ring loop pattern 306a of the first seal ring 306 and the first seal ring loop pattern 706a of the second seal ring 706” and “second seal ring loop pattern 706b surrounding the first seal ring loop pattern 706a”; ¶ 0032 “second seal ring loop pattern 706b surrounding the first seal ring loop pattern 706a” and “first TSVs 200a and these second TSVs 200b are not overlapped with each other” therefore the second dummy vias 200a, 204a are disposed within an inner perimeter of the second seal ring 302b, 702b) of the seal ring (302b, 702b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Chang, US 2022/0262695 (listed in the IDS dated 12-9-2024) in view of Wang et al. (Wang”), US 2022/0254737.
Regarding Claim 6, Chang does not disclose
wherein the second die further comprises second dummy TSVs that extend through the edge regions of the second die,
wherein the second dummy TSVs are not in physical contact with the seal ring.
Wang discloses
wherein the second die (100; Figs. 2C, 3A; ¶ 0014 “100 includes a wafer or a semiconductor substrate and a plurality of active or passive devices formed on the wafer or the semiconductor substrate”) further comprises second dummy TSVs (200a, 204a; Figs. 2C, 3A; ¶ 0018 “TSVs 200 located in the peripheral region PR may be electrically floating”; ¶ 0020 “seal ring 306 is physically in contact with the TSVs 200” and “seal ring 306 is electrically floated” therefore TSVs 200, 200a, 204a are dummy TSVs) that extend through the edge regions (PR; Figs. 2C, 3A; ¶ 0014 “100 includes an active region AR and a peripheral region PR surrounding the active region AR”) of the second die (100),
wherein the second dummy TSVs (200a, 204a) are not in physical contact with (Figs. 2C, 3A; ¶ 0032 “TSVs 200a and these second TSVs 200b are not overlapped with each other”; ¶ 0033 “the first TSVs 200a physically connect the first seal ring loop pattern 306a of the first seal ring 306 and the first seal ring loop pattern 706a of the second seal ring 706, and the second TSVs 200b physically connect the second seal ring loop pattern 306b of the first seal ring 306 and the second seal ring loop pattern 706b of the second seal ring 706” and “first TSVs 200a are disposed corresponding to the first seal ring loop patterns 306a, 706a and the second TSVs 200b are disposed corresponding to the second seal ring loop patterns 306b, 706b. For example, the first TSVs 200a are completely covered/shielded by the first seal ring loop patterns 306a, 706a and the second TSVs 200b are completely covered/shielded by the second seal ring loop patterns 306b, 706b” therefore the second dummy TSVs 200a are not in physical contact with the seal ring 306b, 706b) the seal ring (306b, 302b, 706b, 702b; Figs. 2C, 3A; ¶ 0033 “TSVs 200b physically connect the second seal ring loop pattern 306b of the first seal ring 306 and the second seal ring loop pattern 706b of the second seal ring 706” and “TSVs 200b are completely covered/shielded by the second seal ring loop patterns 306b, 706b”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Chang to have wherein the second die further comprises second dummy TSVs that extend through the edge regions of the second die, wherein the second dummy TSVs are not in physical contact with the seal ring, as taught by Wang, because “as the semiconductor device 110 is sawed or cut at the scribe line 102, the first TSVs 200a may further stop undesirable damage or cracks that escapes through the spacing between two adjacent second TSVs 200b” (Wang ¶ 0033), thereby “further enhancing the structural reinforcement of the semiconductor structure 30” (Wang ¶ 0033) and improving the performance and reliability of the package.
Regarding Claim 7, Chang does not disclose
wherein the second dummy TSVs are disposed adjacent to corner regions of the seal ring, and
wherein in a top-down view, the second dummy TSVs are disposed within an inner perimeter of the seal ring.
Wang discloses
wherein the second dummy TSVs (200a, 204a; Figs. 2C, 3A) are disposed adjacent to corner regions of the seal ring (Fig. 2C; ¶ 0033 “first TSVs 200a and the second TSVs 200b are arranged in a staggered manner”), and
wherein in a top-down view (Fig. 2C; ¶ 0006), the second dummy TSVs are disposed within an inner perimeter of the seal ring (Figs. 2C, 3A; ¶ 0033 “TSVs 200a physically connect the first seal ring loop pattern 306a of the first seal ring 306 and the first seal ring loop pattern 706a of the second seal ring 706” and “second seal ring loop pattern 706b surrounding the first seal ring loop pattern 706a”; ¶ 0032 “second seal ring loop pattern 706b surrounding the first seal ring loop pattern 706a” and “first TSVs 200a and these second TSVs 200b are not overlapped with each other” therefore the second dummy vias 200a, 204a are disposed within an inner perimeter of the second seal ring 302b, 306b, 702b, 706b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Chang to have wherein the second dummy TSVs are disposed adjacent to corner regions of the seal ring, and wherein in a top-down view, the second dummy TSVs are disposed within an inner perimeter of the seal ring, as taught by Wang, because “as the semiconductor device 110 is sawed or cut at the scribe line 102, the first TSVs 200a may further stop undesirable damage or cracks that escapes through the spacing between two adjacent second TSVs 200b” (Wang ¶ 0033), thereby “further enhancing the structural reinforcement of the semiconductor structure 30” (Wang ¶ 0033) and improving the performance and reliability of the package.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (Wang”), US 2022/0254737, in view of Chang, US 2022/0262695 (listed in the IDS dated 12-9-2024).
Regarding Claim 22, Wang does not disclose further comprising a second die over and bonded to the first die.
Chang discloses further comprising a second die (200; Figs 4C, 10F; ¶ 0090 “die 200”) over (¶ 0090 “in a face-to-back configuration”) and bonded to (¶ 0090 “die 200 may be bonded to the first die 100”) the first die (100; Figs. 4C, 10f; ¶ 0090 “die 100”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for wang to have further comprising a second die over and bonded to the first die, as taught by Chang, because “three-dimensional devices provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked chips” (Chang ¶ 0003) thereby improving the performance and reliability of the package.
Allowable Subject Matter
Claim 5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding Claim 5, the prior art does not teach or render obvious wherein a concentration of the first dummy TSVs under corner regions of the seal ring is higher than a concentration of the first dummy TSVs under other regions of the seal ring. Therefore, the combination of Claims 1, 2, 3, and 5 is considered allowable.
Claims 8-15 are allowable.
Regarding Claim 8, the prior art does not disclose a first die comprising: a first substrate; a first interconnect structure on the first substrate; a first seal ring disposed within the first interconnect structure; and first dummy through substrate vias (TSVs) extending through edge regions of the first substrate of the first die, wherein the first dummy TSVs overlap the first seal ring; and a second die disposed below the first die, the first die being bonded to a first side of the second die, the second die comprising: a second substrate; functional TSVs extending through a central region of the second substrate of the second die; a second interconnect structure on the second substrate; a second seal ring disposed within the second interconnect structure; and second dummy TSVs extending through edge regions of the second substrate of the second die, wherein the second dummy TSVs are disposed to be around the functional TSVs and in the combination as claimed.
Claims 9-15 are allowable for depending on Claim 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chiu et al, US 2011/0248404, discloses a package having a substrate, and dummy TSVs extending through the substrate. Lin et al., US 2010/0187671, discloses a package comprising a first die and a second die, the second die having a substrate and a seal ring.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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