Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Invention Group II (Claims 16-20) in the reply filed on May 4, 2026 is acknowledged. Following Applicant’s amendment to the claims, Claims 1-15 are cancelled and Claims 21-35 have been added. Upon review, Examiner finds no new matter has been introduced by the amendment and the new claims fall within the scope of the elected Invention Group II. Therefore an examination on the merits of Claims 16-35 follows.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
--Method Of Manufacturing A BioFET With At Least Two Micro Wells Wherein One Is Higher Than Another--
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16-18 and 21-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Merz (U.S. Pub. 2013/0341734), hereinafter Merz.
Regarding Claim 16, Merz teaches a method of manufacturing a semiconductor structure (‘IC’; Figs. 1(a) – 1(d), Paragraph [0034]), comprising:
-forming a first transistor and a second transistor (e.g. left and center (20); Fig. 1(a), Paragraph [0035]) in a base structure ((10); Fig. 1(a), Paragraph [0035]);
-forming a first dielectric portion (e.g. bottom two (32); Fig. 1(a), paragraph [0037]) over the base structure (10);
-forming a lower part of a first routing (bottom (31) and (33) of left (30); Fig. 1, Paragraph [0036]) in the first dielectric portion (bottom two (32)), the lower part of the first routing (bottom left (31) and (33)) including a first bottom portion (bottom left (31)) which is connected to the first transistor (left (20));
-forming a second routing (center-left (30); Fig. 1(a)) in the first dielectric portion (bottom two (32)), the second routing having a second top portion (center (34); Fig. 1(a), Paragraph [0038]) and a second bottom portion (bottom (31) of center-left (30); Fig. 1(a)) that is connected to the second transistor (center (20));
-forming a second dielectric portion (upper four (32); Fig. 1(a)) over the first dielectric portion (bottom two (32)) to cover the lower part of the first routing (bottom left (31) and (33)) and the second routing (center-left (30));
-forming an upper part of the first routing (left (34) and (34’); Fig. 1(a), Paragraph [0038]) in the second dielectric portion (upper four (32)), the upper part of the first routing including a first top portion (left (34));
-forming a third dielectric portion ((40); Fig. 1(b), Paragraph [0040]) over the second dielectric portion (upper four (32)) to cover the upper part of the first routing (left (34) and (34’));
-forming a first micro well (left (50); Fig. 1(c), Paragraph [0042]) which extends from an upper surface of the third dielectric portion (top of (40); Fig. 1(c)) to expose the first top portion (left (34)); and
-forming a second micro well (center (50); Fig. 1(c)) which extends from the upper surface of the third dielectric portion (top of (40)) through the second dielectric portion (upper four (32); Paragraph [0046]) to expose the second top portion (center (34)).
Regarding Claim 17, Merz teaches a method of manufacturing a semiconductor structure (‘IC’; Figs. 1(a) – 1(d), Paragraph [0034]) of Claim 16, further comprising:
-forming a first sensing layer on an inner surface of the first micro well ((60) within left (50); Fig. 1(d), Paragraph [0050]); and forming a second sensing layer on an inner surface of the second micro well ((60) within center (50)).
Regarding Claim 18, Merz teaches a method of manufacturing a semiconductor structure (‘IC’; Figs. 1(a) – 1(d), Paragraph [0034]) of Claim 16, further comprising:
-forming a third transistor (right (20); Fig, 1(a)) in the base structure (10) before forming the first dielectric portion (bottom two (32)) (structures (30) formed at each level before subsequent dielectric layers (32), Paragraph [0036]);
-forming a lower part of a third routing (bottom (31) and (33) of center-right (30); Fig. 1(a)) in the first dielectric portion (bottom two (32)) before forming the second dielectric portion (upper four (32)), the lower part of the third routing including a third bottom portion (bottom center-right (31)) which is connected to the third transistor (right (20));
-forming an upper part of the third routing (right (34) and (34’); Fig. 1(a)), in the second dielectric portion (upper four (32)) before forming the third dielectric portion (40), the upper part of the third routing including a third top portion (right (30)); and
-forming a pad opening (right (50); Fig. 1(c)) which extends from the upper surface of the third dielectric portion (top of (40)) to expose the third top portion (right (34)).
Regarding Claim 21, Merz teaches a method of manufacturing a semiconductor structure (‘IC’; Figs. 4(a) – 4(c), Paragraph [0063]), comprising:
-forming a first transistor and a second transistor (e.g. left and center (20); Fig. 4(a), Paragraph [0035]) in a base structure ((10); Fig. 4(a), Paragraph [0035]);
-forming a first metal layer (bottom (31) of left (30); Fig. 4(a), Paragraph [0036]) connected to the first transistor (left (20)) and a second metal layer ((36) of right (30); Fig. 4(a), Paragraph [0038])) connected to the second transistor (center (20) (See Paragraph [0073]);
-forming an upper metal layer (left (34); Fig. 4(a), Paragraph [0038]) connected to the first transistor (left (20)) through the first metal layer (bottom left (31));
-depositing a dielectric portion ((40); Fig. 4(a), Paragraph [0040]) over the second metal layer (36) and the upper metal layer (left (34));
-performing a first patterning process on the dielectric portion (40) to form a first micro well (left (50); Fig. 4(b), Paragraph [0042]) exposing the upper metal layer (left (34)) (Examiner notes for the formation of the left (50), this first patterning process includes the formation of (70), Paragraph [0068], separate of the formation of (52)); and
-performing a second patterning process on the dielectric portion (40) to form a second micro well ((52); Fig. 4(b), Paragraph [0042]) exposing the second metal layer (36).
Examiner notes in MPEP 2131, an ipsissmis verbis test isn't required for anticipation, therefore the opening (52) of Merz may be identified as a mico well (the term micro well itself not strictly defined beyond that of a small cavity).
Regarding Claim 22, Merz teaches a method of manufacturing a semiconductor structure (‘IC’; Figs. 4(a) – 4(c), Paragraph [0063]) of Claim 21, further comprising:
- forming a first sensing layer on an inner surface of the first micro well ((60) within left (50); Fig. 4(c), Paragraph [0050]) and a second sensing layer on an inner surface of the second micro well ((60) within (52); Fig. 4(d).
Regarding Claim 23, Merz teaches a method of manufacturing a semiconductor structure (‘IC’; Figs. 4(a) – 4(c), Paragraph [0063]) of Claim 22, wherein:
-the first sensing layer ((60) within left (50)) and the second sensing layer ((60) within (52)) are formed simultaneously (Paragraph [0048]).
Regarding Claim 24, Merz teaches a method of manufacturing a semiconductor structure (‘IC’; Figs. 4(a) – 4(c), Paragraph [0063]) of Claim 22, wherein:
-at least one of the first sensing layer and the second sensing layer includes an electrically conductive material, a dielectric material, a polymeric material, or combinations thereof (e.g. ‘dielectric’ such as Ta2O5 ; Paragraph [0050]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Merz as motivated by Shen et al. (U.S. Pub. 2015/0084099), hereinafter Shen.
Regarding Claim 19, Merz teaches a method of manufacturing a semiconductor structure (‘IC’; Figs. 1(a) – 1(d), Paragraph [0034]) of Claim 18, but does not explicitly incorporate in the exemplary method:
-the first micro well, the second micro well and the pad opening are formed in different processes.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention modify the method of Merz such that the first micro well, the second micro well and the pad opening are formed in different processes. This would be due to the fact that it would be an alternative method of forming completed wells (with the sensing layer) wherein instead of forming all wells at once and subsequently depositing the sensing layer over all of them, each well would be completed prior to a subsequent one. Compare to elements (901) and (1201) of Shen Figs. 11 and 12.
Regarding Claim 20, Merz teaches a method of manufacturing a semiconductor structure (‘IC’; Figs. 1(a) – 1(d), Paragraph [0034]) of Claim 18, but does not explicitly incorporate in the exemplary method:
- the first micro well, the second micro well and the pad opening are respectively formed using different patterning masks.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention modify the method of Merz such that the first micro well, the second micro well and the pad opening are respectively formed using different patterning masks. This would be due to the fact that it would be an alternative method of forming completed wells (with the sensing layer) wherein instead of forming all wells at once and subsequently depositing the sensing layer over all of them, each well would be completed prior to a subsequent one. In order to complete this, different patterning masks would be utilized. Compare to elements (901) and (1201) of Shen Figs. 11 and 12.
Claims 25-28 are rejected under 35 U.S.C. 103 as being unpatentable over Merz in view of Chang et al. (U.S. Pub. 2014/0308752), hereinafter Chang.
Regarding Claim 25, Merz teaches a method of manufacturing a semiconductor structure (‘IC’; Figs. 4(a) – 4(c), Paragraph [0063]) of Claim 21 upon which it depends, but does not teach:
-each of the first metal layer, the second metal layer and the upper metal layer includes an upper film, a lower film and a main body sandwiched between the upper film and the lower film.
Chang teaches a method of manufacturing a semiconductor structure (BioFET (100)/(400); Figs. 1-9, Paragraph [0020] and [0029]) wherein:
-the metal layers (e.g. (403), Fig. 5, Paragraph [0029]) include an upper film, a lower film (upper and lower (419), respectively; Fig. 5, Paragraph [0029]) and a main body (e.g. (405); Fig. 5, Paragraph [0029]) sandwiched between the upper film and the lower film (upper and lower (419))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Chang into the method of Merz such that each of the first metal layer, the second metal layer and the upper metal layer includes an upper film, a lower film and a main body sandwiched between the upper film and the lower film. This would be due to the fact that doing so would incorporate desirable features such as an anti-reflection coating and etch stop layers into the device while maintaining signal conductivity (Chang, Paragraphs [0023] and [0029]).
Regarding Claim 26, Merz as modified by Chang teaches a method of manufacturing a semiconductor structure (‘IC’; Figs. 4(a) – 4(c), Paragraph [0063]) of Claim 25, wherein:
-the upper film and the lower film (Chang, upper and lower (419), respectively) include titanium, titanium nitride, or a combination thereof (Chang, Paragraph [0029]).
Regarding Claim 27, Merz as modified by Chang teaches a method of manufacturing a semiconductor structure (‘IC’; Figs. 4(a) – 4(c), Paragraph [0063]) of Claim 25, wherein:
- the main body (Chang, (405)) includes aluminum copper, aluminum, copper, tungsten, or combinations thereof (aluminum, copper, or tungsten’ Paragraph [0028]).
Regarding Claim 28, Merz as modified by Chang teaches a method of manufacturing a semiconductor structure (‘IC’; Figs. 4(a) – 4(c), Paragraph [0063]) of Claim 25, wherein:
-the first micro well (Merz, left (50)) extends downwardly from an upper surface of the dielectric portion (Merz, (40)) into the upper film of the upper metal layer (Merz as modified by Chang, left (34)) and has a first height (‘H1’ taken from the surface of (10) to bottom of left (50); Fig. 4(c)); and
-the second micro well (Merz, (52)) extends downwardly from the upper surface of the dielectric portion (Merz, (40)) into the upper film of the second metal layer (Merz as modified by Chang, (36)) and has a second height (‘H2’ taken from the surface of (10) to the bottom of (52); Fig. 4(c)) greater than the first height (H1).
Examiner notes that even if “height” is amended to be defined as from the bottom of the micro wells to the surface of the dielectric portion, the limitation would still be taught by Merz by simply changing the interpretation of which well is the first vs second.
Allowable Subject Matter
Claims 29-35 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 29, the best prior art of record does not teach or fairly suggest, along with the other claimed features, which are necessary in establishing the methodology, a method of manufacturing a semiconductor device comprising:
- forming a lower part of a first routing and a second routing in the first dielectric portion simultaneously
- forming an upper part of the first routing in the second dielectric portion
-the second micro well having a second accommodation volume larger than the first accommodation volume.
Regarding Claims 30-35, the claim are allowable based on their dependence on Claim 29.
Closest prior art references found during examination are listed below:
U.S. Pub. 2013/0341734 U.S. Pub. 2014/0308752 U.S. Pub. 2015/0084099
These references disclose similar methods of manufacturing a semiconductor structure (BioFET) intended to serve as biosensors. However, none of the references disclose a method wherein there is a distinct formation of a lower part of a first routing and a whole second routing (notably including the second top portion of which the second micro well is opened to), followed by the formation of an upper part of the first routing structure. Based on this chronological ordering, and the necessity of the second micro well having a second accommodation volume larger than the first accommodation volume, one of ordinary skill of the art would not find a obvious reason to modify previously disclosed methods.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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/DMITRI MIHALIOV/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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