DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 23 and 25 are objected to because of the following informalities:
Claim 23 reads “…further includes an electrical isolation structure that extends in the first horizontal direction and that insects with the portions of the one or more gate structures…”
Claim 25 reads “…a distance between the second boundary and the first FTVs…” however claim 22, which claim 25 depends on, defines a first feedthrough via (FTV), not a plurality.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8 and 22-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su et al. (“Su” US 2020/0395476).
Regarding claim 8, Su discloses an integrated circuit (IC) layout (Figures 1-4), comprising:
a memory region (106), wherein the memory region includes a plurality of memory cells (120, see Figure 2), and wherein each of the memory cells has a first dimension in a first horizontal direction (Y-direction labeled in the Figures, here the first dimension of the cell is the width of the cell between the gates 220 in the first direction/Y-direction); and
an edge region (104) bordering the memory region (106, see Figure 1) in the first horizontal direction (Y-direction), wherein the edge region (104) includes a dielectric isolation structure (231) that extends in a second horizontal direction (X-direction labeled in the Figures) different from the first horizontal direction (Y-direction).
Regarding claim 22, Su discloses wherein the edge region (104) further includes:
one or more gate structures (220) that extend in the second horizontal direction (X-direction, see Figure 3, although the gate structures 220 are 3D objects, thus extend in the X, Y, and Z directions); and
a first feedthrough via (FTV) (240 left group, i.e. upper left group of vias 240 in Figure 3) and a second FTV (240, upper right group) that extend in the first horizontal direction (Y-direction);
wherein portions of the one or more gate structures (220) are disposed between the first FTV (240, left group) and the second FTV (240, right group) in the second horizontal direction (Y-direction, see Figure 3).
Regarding claim 23, Su discloses wherein the edge region (104) further includes an electrical isolation structure (230) that extends in the first horizontal direction (Y-direction) and that insects with the portions of the one or more gate structures (220) disposed between the first FTV (240, left group) and the second FTV (240, right group, see Figure 3).
Regarding claim 24, Su discloses wherein the edge region (104) further includes a plurality of active regions (210) that extend in the first horizontal direction (Y-direction), and wherein in a top view defined by the first horizontal direction and the second horizontal direction (see Figure 3), no portions of the active regions (210) are disposed directly between the dielectric isolation structure (231) and the first FTV (240, left group) or between the dielectric isolation structure (231) and the second FTV (240, right group, see Figure 3).
Regarding claim 25, Su discloses wherein:
the edge region (104) has a first boundary (line coplanar with lower edges of the electrical isolation structure 230 and active regions 210 in Figure 3, extending in the X-direction) that borders the memory region (106) and a second boundary (line coplanar with upper edges of the electrical isolation structure 230 and active regions 210 in Figure 3, extending in the X-direction) opposite the first boundary (see annotated Figure 3 below);
the first boundary and the second boundary extend in the second horizontal direction (X-direction, see Figure 3); and
a distance between the second boundary (line coplanar with upper edges of the electrical isolation structure 230 and active regions 210 in Figure 3) and the first FTVs (240) is less than the first dimension (the first dimension is the distance between two adjacent gates 220, and the distance between the uppermost first FTV 240, left group, and the second boundary is less than the distance between two adjacent gates 220, see annotated Figure 3 below).
Regarding claim 26, Su further discloses a periphery region that includes input/output devices, logic devices, or drivers configured to control or operate the memory cells of the memory region, wherein the edge region (104) is disposed between the memory region (106) and the periphery region in the first horizontal direction (see Figure 1, para. [0016]).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 27-30 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (“Su” US 2020/0395476) and Pao et al. (“Pao” US 2019/0096474).
Regarding claim 1, Su teaches a device (Figures 1-4), comprising:
a memory region (106), wherein the memory region includes a plurality of memory cells (120, see Figure 2), and wherein each of the memory cells has a first dimension in a first horizontal direction (Y-direction labeled in the Figures, here the first dimension of the cell is the width of the cell between the gates 220 in the first direction/Y-direction); and
an edge region (104) bordering the memory region (106, see Figure 1) in the first horizontal direction (Y-direction), the edge region (104) having a first border (line coplanar with lower edges of the electrical isolation structure 230 and active regions 210 in Figure 3, extending in the X-direction) that borders the memory region (106) and a second border (line coplanar with upper edges of the electrical isolation structure 230 and active regions 210 in Figure 3, extending in the X-direction) opposite the first border (see annotated Figure 3 below), wherein the first border and the second border each extend in a second horizontal direction (X-direction, labeled in the Figures) different from the first horizontal direction (Y-direction), wherein the edge region (104) has a second dimension that extends from the first border to the second border in the first horizontal direction (Y-direction, see Figure 3).
Su does not teach wherein the second dimension is less than or equal to about 4 times the first dimension.
Pao teaches an edge region (“strap region”, para. [0071]) with a second dimension (length) less than or equal to about 4 times the first dimension (gate pitch, para. [0071], Pao teaches that the second dimension, the length of the strap region, is less than six times the first dimension, the gate pitch).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Pao into the teachings of Su to include the claimed relative dimensions for the purpose of reducing resistance of well regions (Pao, para. [0071]).
Note that the range disclosed by Pao overlaps the claimed range. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art,” a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)). Additionally, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the relative dimensions to be a result effective variable affecting resistance. Thus, it would have been obvious to modify the device of Su to have the dimensions within the claimed range in order to reduce well resistance, and since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05 II.B and 2143.
Regarding claim 2, Pao teaches wherein the second dimension is equal to about 4 times the first dimension, about 3.5 times the first dimension, about 3 times the first dimension, about 2.5 times the first dimension, or about 2 times the first dimension (less than 6 times, see para. [0071]).
Regarding claim 3, Su teaches wherein the edge region (104) includes:
a plurality of feedthrough vias (FTVs) (240) that are disposed relative to one another in the second horizontal direction (X-direction labeled in the Figures, see Figure 3), wherein the second horizontal direction is perpendicular to the first horizontal direction (X-direction is perpendicular to the Y-direction); and
a dielectric isolation (208) structure that extends in the second horizontal direction (X-direction, see Figure 4).
Regarding claim 4, Su teaches the edge region (104) further includes a first active region and a second active region (active regions 210) that each extend in the first horizontal direction (Y-direction, see Figure 3, the first active region is the leftmost active region protrusion/fin 210 in Figure 4, the second active region being the second leftmost active region protrusion/fin 210 in Figure 4);
the first active region (210, leftmost fin in Figure 4) is directly abutted to a first side of the dielectric isolation structure (208, see Figure 4, direct contact between a side of the dielectric isolation structure and the first active region); and
the second active region (210, second leftmost fin in Figure 4) is directly abutted to a second side of the dielectric isolation structure (208, see Figure 4, direct contact between a side of the dielectric isolation structure and the second active region).
Regarding claim 5, Su teaches wherein:
the edge region has a first border (line coplanar with lower edges of the electrical isolation structure 230 and active regions 210 in Figure 3, extending in the X-direction) that borders the memory region (106) and a second border (line coplanar with upper edges of the electrical isolation structure 230 and active regions 210 in Figure 3, extending in the X-direction) opposite the first border (see annotated Figure 3 below);
the first border and the second border each extend in the second horizontal direction (X-direction, see Figure 3); and
a distance between the second border (line coplanar with upper edges of the electrical isolation structure 230 and active regions 210 in Figure 3) and one of the FTVs is less than the first dimension (the first dimension is the distance between two adjacent gates 220, and the distance between the uppermost FTV 240 and the second border is less than the distance between two adjacent gates 220, see annotated Figure 3 below).
Regarding claim 27, Su further teaches a periphery region that includes input/output devices, logic devices, or drivers (see para. [0016]) configured to control or operate the memory cells of the memory region (106), wherein the edge region (104) is disposed between the memory region (1060 and the periphery region in the first horizontal direction (see Figure 1, para. [0016]).
Regarding claim 28, Su teaches a device (Figures 1-4), comprising:
a memory region (106) that includes a plurality of Static Random Access Memory (SRAM) cells (see Figures 1, 2), and wherein at least one of the SRAM cells has a first dimension in a first horizontal direction (labeled Y-direction in the Figures, here the first dimension is the distance between two adjacent gates 220 shown in Figure 2); and
an edge region (104) that at least partially surrounds the memory region (106, see Figure 1), wherein the edge region is free of the SRAM cells (see Figure 3) and includes a plurality of feedthrough vias (FTVs) (240) that extend in the first horizontal direction (Y-direction) and a dielectric isolation structure (208) that extends in a second horizontal direction (X-direction) different from the first horizontal direction (Y-direction, see Figure 4), wherein the edge region has a second dimension in the first horizontal direction (distance between borders/boundaries in annotated Figure 3 below).
Su does not teach wherein the second dimension is less than or equal to about 4 times the first dimension.
Pao teaches an edge region (“strap region”, para. [0071]) with a second dimension (length) less than or equal to about 4 times the first dimension (gate pitch, para. [0071], Pao teaches that the second dimension, the length of the strap region, is less than six times the first dimension, the gate pitch).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Pao into the teachings of Su to include the claimed relative dimensions for the purpose of reducing resistance of well regions (Pao, para. [0071]).
Note that the range disclosed by Pao overlaps the claimed range. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art,” a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)). Additionally, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the relative dimensions to be a result effective variable affecting resistance. Thus, it would have been obvious to modify the device of Su to have the dimensions within the claimed range in order to reduce well resistance, and since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05 II.B and 2143.
Regarding claim 29, Su teaches the edge region (104) further includes a first active region (leftmost active region protrusion/fin 210 in Figure 4) and a second active region (leftmost active region protrusion/fin 210 in Figure 4) that extend in the first horizontal direction (Y-direction, see Figure 3);
the first active region (leftmost active region protrusion/fin 210 in Figure 4) extends to a first side of the dielectric isolation structure (208, see Figure 4); and the second active region (second leftmost active region protrusion/fin 210 in Figure 4) extends to a second side of the dielectric isolation structure (208) opposite the first side (see Figure 4).
Regarding claim 30, Su teaches wherein:
the edge region (104) has a first border (line coplanar with lower edges of the electrical isolation structure 230 and active regions 210 in Figure 3, extending in the X-direction) that borders the memory region (106) and a second border (line coplanar with upper edges of the electrical isolation structure 230 and active regions 210 in Figure 3, extending in the X-direction) opposite the first border (see annotated Figure 3 below);
the first border and the second border each extend in the second horizontal direction (X-direction, see Figure 3); and
a distance between the second border (line coplanar with upper edges of the electrical isolation structure 230 and active regions 210 in Figure 3) and one of the FTVs (uppermost 240 in Figure 3) is less than the first dimension (the first dimension is the distance between two adjacent gates 220, and the distance between the uppermost FTV 240 and the second border is less than the distance between two adjacent gates 220, see annotated Figure 3 below).
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Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Su as applied to claim 8 above, and further in view of Pao et al. (“Pao” US 2019/0096474).
Regarding claim 21, Su does not teach wherein the edge region has a second dimension in the first horizontal direction, and wherein the second dimension is less than or equal to about 4 times the first dimension.
Pao teaches an edge region (“strap region”, para. [0071]) with a second dimension (length) less than or equal to about 4 times the first dimension (gate pitch, para. [0071], Pao teaches that the second dimension, the length of the strap region, is less than six times the first dimension, the gate pitch).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Pao into the teachings of Su to include the claimed relative dimensions for the purpose of reducing resistance of well regions (Pao, para. [0071]).
Note that the range disclosed by Pao overlaps the claimed range. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art,” a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)). Additionally, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the relative dimensions to be a result effective variable affecting resistance. Thus, it would have been obvious to modify the device of Su to have the dimensions within the claimed range in order to reduce well resistance, and since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05 II.B and 2143.
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Response to Arguments
Applicant’s arguments with respect to claims 1, 8, 28, and the dependent claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s amendments with respect to the 112(a) rejection of claim 24 have been fully considered and are persuasive. The 112(a) rejection of claim 24 has been withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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