DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, and Species 1a and 2a in the reply filed on March 12 2026 is acknowledged.
Claims 6-7 and 9-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant has cancelled claims 11-20 which were drawn to a nonelected invention. Election was made without traverse in the reply filed on March 12 2026. Thus, claims 1-5, 8, and 21-30 are examined.
The Restriction/Election Requirement is made final.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 24 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 24 requires the limitation “wherein the edge region further includes a plurality of active regions that extend in the first horizontal direction, and wherein no portions of the active regions are disposed directly between the dielectric isolation structure and the first FTV or between the dielectric isolation structure and the second FTV”. However, Applicant has not adequately disclosed this feature in the instant specification. Negative limitations must be positively recited in the specification. Further, support may be suggested by the drawings, however the drawings only show the top view of the device, thus it is not certain that the active regions may be between the dielectric isolation structure and the first and second FTVs in other perspective or cross-sectional views of the device. Thus, new matter has been introduced into the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8, 21-22, and 24-30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang et al. (“Wang” US 2024/0306361).
Regarding claim 1, Wang discloses a device (Figure 11), comprising:
a memory region (portion of the SRAM cell block shown in Figure 11 with the SRAM cells therein, i.e. the portion to the left of the transition region 370 in Figure 11), wherein the memory region (SRAM cell region) includes a plurality of memory cells (SRAM cells, see Figure 11), and wherein each of the memory cells has a first dimension (here a “first dimension” is a broad term which does not necessarily require the entire width/thickness of the memory cell, which is 2 poly pitches PP, see para. [0032], thus the first dimension may be arbitrarily chosen to be, for example, 1.5 poly pitches PP) in a first horizontal direction (X direction in Figure 11); and
an edge region (transition region 370) bordering the memory region (SRAM cell region) in the first horizontal direction (X direction, see Figure 11), wherein the edge region (370) has a second dimension (the edge region has a total width of three poly pitches PP, see para. [0060]) in the first horizontal direction (X direction, see Figure 11), and wherein the second dimension (three PP) is less than or equal to about 4 times the first dimension (1.5 PP, see Figure 11).
Regarding claim 2, Wang discloses wherein the second dimension (3 PP) is equal to about 4 times the first dimension, about 3.5 times the first dimension, about 3 times the first dimension, about 2.5 times the first dimension, or about 2 times the first dimension (1.5 PP, see above).
It is the Examiner’s position that the term “dimension” does not require the entire thickness, width, or length of an element, and may be arbitrarily chosen in the prior art to meet the claim limitation above.
Regarding claim 3, Wang discloses wherein the edge region includes a plurality of feedthrough vias (FTVs) (rightmost “gate structures” 340 in the edge cell region 370 next to the logic cells, these gate structures are considered feed through vias because they extend through the device like a via in the art) that are disposed relative to one another in a second horizontal direction (Y direction in Figure 11) perpendicular to the first horizontal direction (X direction in Figure 11); and
a dielectric isolation structure (374) that extends in the second horizontal direction (Y direction, see Figure 11).
Regarding claim 4, Wang discloses the edge region (370) further includes a first active region (305A) and a second active region (305B, mislabeled in Figure 11 as 350B) that each extend in the first horizontal direction (X direction in Figure 11);
the first active region (305A) is directly abutted to a first side (left side in Figure 11) of the dielectric isolation structure (374, see Figure 11);
and the second active region (305B) is directly abutted to a second side (right side in Figure 11) of the dielectric isolation structure (374, see Figure 11).
Regarding claim 5, Wang discloses the edge region (370) has a first border (left side border in Figure 11) that borders the memory region (SRAM cell region) and a second border (right side border) opposite the first border (left side border);
the first border (left side border) and the second border (right side border) each extend in the second horizontal direction (Y direction, see Figure 11); and
a distance between the second border (right side border) and one of the FTVs (rightmost gate structures 340) is less than the first dimension (Figure 11 clearly shows the distance between the right side border and the rightmost gate structures is less than 1.5 PP).
Regarding claim 8, Wang discloses an integrated circuit (IC) layout (Figure 11), comprising:
a memory region (SRAM cell region, see Figure 11), wherein the memory region (SRAM cell region) includes a plurality of memory cells (SRAM cells, see Figure 11), and wherein each of the memory cells (SRAM cells) has a first dimension (here a “first dimension” is a broad term which does not necessarily require the entire width/thickness of the memory cell, which is 2 poly pitches PP, see para. [0032], thus the first dimension may be arbitrarily chosen to be, for example, 1.5 poly pitches PP) in a first horizontal direction (X direction in Figure 11); and
an edge region (transition region 370) bordering the memory region (SRAM cell region) in the first horizontal direction (X direction, see Figure 11), wherein the edge region (370) includes a dielectric isolation structure (374) that extends in a second horizontal direction (Y direction in Figure 11) different from the first horizontal direction (Y direction is different from the X direction, see Figure 11).
Regarding claim 21, Wang discloses wherein the edge region (370) has a second dimension (the edge region has a total width of three poly pitches PP, see para. [0060]) in the first horizontal direction (X direction, see Figure 11), and wherein the second dimension (three PP) is less than or equal to about 4 times the first dimension (1.5 PP, see Figure 11).
It is the Examiner’s position that the term “dimension” does not require the entire thickness, width, or length of an element, and may be arbitrarily chosen in the prior art to meet the claim limitation above.
Regarding claim 22, Wang discloses wherein the edge region (370) further includes:
one or more gate structures (352, portions extend into the edge cell region 370, thus are considered as included in the edge cell region 370) that extend in the second horizontal direction (Y direction, the gate structure 352 have a thickness in the Y direction, thus are considered as extending in the second horizontal direction); and
a first feedthrough via (FTV) (rightmost gate structures 340 in the edge cell region 370 next to the logic cells, these gate structures are considered feed through vias because they extend through the device like a via in the art, here the first FTV is considered as the upper right FTV 340 in Figure 11) and a second FTV (FTV 340 directly below the first FTV 340, see also annotated Figure 11 below) that extend in the first horizontal direction (the FTVs 340 have a thickness in the X direction, thus are considered as extending in the first horizontal X direction);
wherein portions of the one or more gate structures (352) are disposed between the first FTV (top right 340) and the second FTV (340 below top right 340 in Figure 11) in the second horizontal direction (Y direction, see Figure 11 which shows a gate structure 352 between the two FTVs in the Y direction).
Regarding claim 24, Wang discloses wherein the edge region (370) further includes a plurality of active regions (305A) that extend in the first horizontal direction (X direction in Figure 11), and wherein no portions of the active regions (305A) are disposed directly between the dielectric isolation structure (374) and the first FTV (upper right FTV 340) or between the dielectric isolation structure (374) and the second FTV (FTV 340 directly below the first FTV, see Figure 11 which shows the active region 305A on the opposite side of the dielectric isolation structure 374 than the side of the dielectric isolation structure 374 that the FTVs are on, thus the active regions are not therebetween).
Regarding claim 25, Wang discloses the edge region (370) has a first boundary (left side border in Figure 11) that borders the memory region (SRAM cell region) and a second boundary (right side border) opposite the first boundary (left side border);
the first boundary (left side border) and the second boundary (right side border) extend in the second horizontal direction (Y direction, see Figure 11); and
a distance between the second boundary (right side border) and one of the FTVs (rightmost gate structures 340) is less than the first dimension (Figure 11 clearly shows the distance between the right side border and the rightmost gate structures is less than 1.5 PP).
Regarding claim 26, Wang further discloses a periphery region (logic region with logic cells, see Figure 11) that includes input/output devices, logic devices (logic cells), or drivers configured to control or operate the memory cells of the memory region (SRAM cell region, see para. [0017]), wherein the edge region (370) is disposed between the memory region (SRAM cell region) and the periphery region (logic cell region) in the first horizontal direction (X direction, see Figure 11).
Regarding claim 27, Wang further discloses a periphery region (logic region with logic cells, see Figure 11) that includes input/output devices, logic devices (logic cells), or drivers configured to control or operate the memory cells of the memory region (SRAM cell region, see para. [0017]), wherein the edge region (370) is disposed between the memory region (SRAM cell region) and the periphery region (logic cell region) in the first horizontal direction (X direction, see Figure 11).
PNG
media_image1.png
630
975
media_image1.png
Greyscale
Regarding claim 28, Wang discloses a device (Figure 11), comprising:
a memory region (SRAM cell region) that includes a plurality of Static Random Access Memory (SRAM) cells (see SRAM cells in Figure 11), and wherein at least one of the SRAM cells has a first dimension (here a “first dimension” is a broad term which does not necessarily require the entire width/thickness of the memory cell, which is 2 poly pitches PP, see para. [0032], thus the first dimension may be arbitrarily chosen to be, for example, 1.5 poly pitches PP) in a first horizontal direction (X direction in Figure 11); and
an edge region (transition region 370) that at least partially surrounds the memory region (SRAM cell region, see Figure 11), wherein the edge region (370) is free of the SRAM cells (see Figure 11, there are no SRAM cells in the edge cell region 370) and includes a plurality of feedthrough vias (FTVs) (rightmost “gate structures” 340 in the edge cell region 370 next to the logic cells, these gate structures are considered feed through vias because they extend through the device like a via in the art) that extend in the first horizontal direction (X direction, since the FTVs have a thickness in the X direction, they are considered as extending in the first horizontal, or X, direction) and a dielectric isolation structure (374) that extends in a second horizontal direction (Y direction in Figure 11) different from the first horizontal direction (X direction in Figure 11, see Figure 11), wherein the edge region (370) has a second dimension (the edge region has a total width of three poly pitches PP, see para. [0060]) in the first horizontal direction (X direction, see Figure 11), and wherein the second dimension (three PP) is less than or equal to about 4 times the first dimension (1.5 PP, see Figure 11).
It is the Examiner’s position that the term “dimension” does not require the entire thickness, width, or length of an element, and may be arbitrarily chosen in the prior art to meet the claim limitation above.
Regarding claim 29, Wang discloses the edge region (370) further includes a first active region (305A) and a second active region (305B, mislabeled in Figure 11 as 350B) that extend in the first horizontal direction (X direction, see Figure 11);
the first active region (305A) extends to a first side (left side in Figure 11) of the dielectric isolation structure (374, see Figure 11); and the second active region (305B) extends to a second side (right side in Figure 11) of the dielectric isolation structure (374) opposite the first side (left side, see Figure 11).
Regarding claim 30, Wang discloses the edge region (370) has a first border (left side border in Figure 11) that borders the memory region (SRAM cell region) and a second border (right side border) opposite the first border (left side border);
the first border (left side border) and the second border (right side border) extend in the second horizontal direction (Y direction, see Figure 11); and
a distance between the second border (right side border) and one of the FTVs (rightmost gate structures 340) is less than the first dimension (Figure 11 clearly shows the distance between the right side border and the rightmost gate structures is less than 1.5 PP).
Alternatively, claims 1-2, 8, 21, and 28 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by the disclosed prior art in at least Figures 4A and 4C of the instant application.
It is the Examiner’s position that the disclosed “original IC layout” has been made part of the disclosure as admitted prior art. Applicant has labeled Figures 4A-21A as “original IC layouts” (see at least para. [0008], [0026], [0039]), which suggests that the disclosed IC layouts of Figures 4A-21A existed before the effective filing date of the present invention. The present invention, moreover, is drawn to Figures 4B-21B, labeled/named the “revised IC layout”. Thus further concludes that the “original IC layouts” are admitted prior art, upon which the present invention (“revised IC layout”) is an improvement.
Regarding claim 1, The admitted prior art (Figures 4A/4C) discloses a device, comprising:
a memory region (120A), wherein the memory region (120A) includes a plurality of memory cells (320), and wherein each of the memory cells (320) has a first dimension (width SRM) in a first horizontal direction (X direction in Figure 4A); and
an edge region (120B) bordering the memory region (120A) in the first horizontal direction (X direction in Figure 4A), wherein the edge region (120B) has a second dimension (distance between gate structure 230 and gate structure directly to the right of the FTV 130) in the first horizontal direction (X direction in Figure 4A), and wherein the second dimension (distance between gate structure 230 and gate structure directly to the right of the FTV 130) is less than or equal to about 4 times the first dimension (SRM, which is equal to 2 CPP, where the second dimension is equal to 7 CPP, thus the second dimension 7 CPP is less than 4 time 2 CPP).
It is the Examiner’s position that the term “dimension” does not require the entire thickness, width, or length of an element, and may be arbitrarily chosen in the prior art to meet the claim limitation above.
Regarding claim 2, The admitted prior art discloses wherein the second dimension (7 CPP) is equal to about 4 times the first dimension, about 3.5 times the first dimension (3.5 times 2 CPP is 7CPP), about 3 times the first dimension, about 2.5 times the first dimension, or about 2 times the first dimension.
Regarding claim 8, The admitted prior art discloses an integrated circuit (IC) layout (Figure 4A/4C), comprising:
a memory region (120A), wherein the memory region (120A) includes a plurality of memory cells (320), and wherein each of the memory cells (320) has a first dimension (width SRM) in a first horizontal direction (X direction in Figure 4A); and
an edge region (120B) bordering the memory region (120A) in the first horizontal direction (X direction in Figure 4A), wherein the edge region (120B) includes a dielectric isolation structure (300, see para. [0033]) that extends in a second horizontal direction (Y direction) different from the first horizontal direction (X direction, see Figure 4A).
Regarding claim 21, The admitted prior art (Figures 4A/4C) discloses wherein the edge region (120B) has a second dimension (distance between gate structure 230 and gate structure directly to the right of the FTV 130) in the first horizontal direction (X direction in Figure 4A), and wherein the second dimension (distance between gate structure 230 and gate structure directly to the right of the FTV 130) is less than or equal to about 4 times the first dimension (SRM, which is equal to 2 CPP, where the second dimension is equal to 7 CPP, thus the second dimension 7 CPP is less than 4 time 2 CPP).
It is the Examiner’s position that the term “dimension” does not require the entire thickness, width, or length of an element, and may be arbitrarily chosen in the prior art to meet the claim limitation above.
Regarding claim 28, The admitted prior art discloses a device (Figure 4A/4C), comprising:
a memory region (120A) that includes a plurality of Static Random Access Memory (SRAM) cells (320, see Figure 4A/4C), and wherein at least one of the SRAM cells has a first dimension (SRM) in a first horizontal direction (X direction, see Figure 4A); and
an edge region (120B) that at least partially surrounds the memory region (120A), wherein the edge region (120B) is free of the SRAM cells (320, see Figure 4A) and includes a plurality of feedthrough vias (FTVs) (320) that extend in the first horizontal direction (X direction) and a dielectric isolation structure (300) that extends in a second horizontal direction (Y direction in Figure 4A) different from the first horizontal direction (X direction), wherein the edge region (120B) has a second dimension (distance between gate structure 230 and gate structure directly to the right of the FTV 130) in the first horizontal direction (X direction in Figure 4A), and wherein the second dimension (distance between gate structure 230 and gate structure directly to the right of the FTV 130) is less than or equal to about 4 times the first dimension (SRM, which is equal to 2 CPP, where the second dimension is equal to 7 CPP, thus the second dimension 7 CPP is less than 4 time 2 CPP).
It is the Examiner’s position that the term “dimension” does not require the entire thickness, width, or length of an element, and may be arbitrarily chosen in the prior art to meet the claim limitation above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 22 above, and further in view of Su et al. (“Su” US 2020/0395476).
Regarding claim 23, Wang does not disclose wherein the edge region further includes an electrical isolation structure that extends in the first horizontal direction and that insects with the portions of the one or more gate structures disposed between the first FTV and the second FTV.
Su discloses, however, the edge region (104, see Figures 1 and 3) further includes an electrical isolation structure (230) that extends in the first horizontal direction (Y direction in Figure 3) and that insects with the portions of the one or more gate structures (220, see Figure 3) disposed between the first FTV (top left group of contacts 240 in the left sided P well region 204 when viewing Figure 3) and the second FTV (top right group of contacts 240 in the middle P well region when viewing Figure 3).
It would have been obvious to incorporate the teachings of Su into the teachings of Wang to include the electrical isolation structure as taught by Su for the purpose of providing electrical isolation between boundaries of the device, as well as to separate gate structures (Su, para. [0018]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights