Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-13 and 17-22 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Chang (US 20180068983 A1).
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Regarding claim 1, Chang discloses an electronic package (Fig. 2F'), comprising: a circuit structure (see attached figure) having a circuit layer (layer of circuitry within circuit structure) and a first side (upper side of circuit structure) and a second side opposing the first side (lower side of circuit structure); an electronic component (21) disposed on the first side of the circuit structure and electrically connected to the circuit layer (Shown); and a thermally conductive chip (Comprises 29, 91, ad portions of 201 connected to pillars 23; para. 47 "the shielding layer 29 is made of metal", metals are well known to be thermally conductive) disposed on the electronic component (Shown), wherein the electronic component is sandwiched between the circuit structure and the thermally conductive chip (Fig. 2F' shows metal bumps 212 connecting electronic component 21 to circuit structure; metal bumps labeled in Fig. 2C), wherein the thermally conductive chip has a plurality of conductive vias penetrating through the thermally conductive chip (instances of 201 shown connected to pillars 23).
Regarding claim 2, Chang discloses further comprising a plurality of conductive pillars (conductive pillar 23) disposed between the first side of the circuit structure and the thermally conductive chip and electrically connected to the circuit layer (Shown).
Regarding claim 3, Chang discloses wherein the thermally conductive chip has a plurality of conductive vias (Fig. 2F', 201; para. 30 "201 is made of copper", which is well known to be conductive), and the plurality of conductive vias are electrically connected to the circuit layer via the plurality of conductive pillars (Fig. 2F' shows conductive pillars in electrical contact with conductive vias 201).
Regarding claim 4, Chang discloses wherein the electronic component is disposed on the first side of the circuit structure via a plurality of conductive bumps (Fig. 2F' shows metal bumps 212 connecting electronic component 21 to circuit structure; metal bumps labeled in Fig. 2C).
Regarding claim 5, Chang discloses further comprising an encapsulation layer (25) formed between the first side of the circuit structure and the thermally conductive chip and covering the electronic component and the plurality of conductive pillars (shown).
Regarding claim 6, Chang discloses wherein the electronic component is disposed on the first side of the circuit structure via a plurality of conductive bumps (Fig. 2F' shows metal bumps 212 connecting electronic component 21 to circuit structure; metal bumps labeled in Fig. 2C), and an underfill covering the plurality of conductive bumps (211, labeled in Fig. 2B) is further formed between the electronic component and the first side of the circuit structure (Shown).
Regarding claim 7, Chang discloses wherein the electronic component is disposed on the first side of the circuit structure (Shown) via a plurality of conductive bumps (Fig. 2F' shows metal bumps 212 connecting electronic component 21 to circuit structure; metal bumps labeled in Fig. 2C), and an encapsulation layer (25) covering the plurality of conductive bumps, the electronic component and the plurality of conductive pillars is formed between the thermally conductive chip and the first side of the circuit structure (Fig. 2F' shows encapsulation layer 25, electronic component 21, and plurality of conductive pillars 23 formed between thermally conductive chip 29 and upper surface of circuit structure).
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Regarding claim 8, Chang discloses further comprising at least one functional component and at least one conductive component disposed on the second side of the circuit structure (See attached figure).
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Regarding claim 9, Chang discloses further comprising a heat dissipation material (portions of 201, see attached figure; para. 30 "201 is made of copper", which is known to be a good heat conductor/dissipator) formed between the thermally conductive chip and the electronic component (Shown).
Regarding claim 10, Chang discloses further comprising at least one functional component disposed on the thermally conductive chip (Comprises 20 and 91, shown disposed on the bottom surface of thermally conductive chip 29).
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Regarding claim 11, Chang discloses a method of manufacturing an electronic package, comprising: providing a thermally conductive chip (Fig. 2F'; comprises 29, 91, and portions of 201 connected to pillars 23; para. 46 "a shielding layer 29 is formed on the packaging layer 24"), an electronic component (Fig. 2A, 21) and a circuit structure (Fig. 2C, see attached figure), wherein the circuit structure has a circuit layer (layer of circuitry within circuit structure) and a first side (upper side of circuit structure) and a second side opposing the first side (lower side of circuit structure); and disposing the electronic component between the first side of the circuit structure and the thermally conductive chip (Shown in Fig. 2F'), wherein the electronic component is electrically connected to the circuit layer (Fig. 2F' shows metal bumps 212 connecting electronic component 21 to circuit structure; metal bumps labeled in Fig. 2C), wherein the thermally conductive chip has a plurality of conductive vias penetrating through the thermally conductive chip (instances of 201 shown connected to pillars 23).
Regarding claim 13, Chang discloses further comprising forming a plurality of conductive pillars (Fig. 2F', 23) on the thermally conductive chip (Fig. 2F' shows conductive pillars 23 on portion 201 of thermally conductive chip), wherein the plurality of conductive pillars are electrically connected to the plurality of conductive vias (Fig. 2F' shows conductive pillars in electrical contact with conductive vias 201).
Regarding claim 17, Chang discloses wherein the electronic component formed with a plurality of conductive bumps is disposed on the thermally conductive chip (Shown in figs. 2E and 2F').
Regarding claim 18, Chang discloses further comprises forming an encapsulation layer (25) on the thermally conductive chip to cover the electronic component, the plurality of conductive pillars and the plurality of conductive bumps (Shown in Fig. 2F'), wherein end surfaces of the plurality of conductive pillars and end surfaces of the plurality of conductive bumps are exposed from the encapsulation layer (Fig. 2F' shows conductive pillars 23 not being covered by encapsulation 25).
Regarding claim 19, Chang discloses wherein the plurality of conductive pillars and the plurality of conductive bumps are disposed on the first side of the circuit structure, and the circuit layer is electrically connected to the plurality of conductive pillars and the plurality of conductive bumps (Shown in Fig. 2F').
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Regarding claim 20, Chang discloses further comprising arranging at least one functional component and at least one conductive component on the second side of the circuit structure (See attached figure).
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Regarding claim 21, Chang discloses wherein the thermally conductive chip and the electronic component have a heat dissipation material formed therebetween (portions of 201, see attached figure; para. 30 "201 is made of copper", which is known to be a good heat conductor/dissipator).
Regarding claim 22, Chang discloses wherein at least one functional component is disposed on the thermally conductive chip (Comprises 20 and 91, shown disposed on the bottom surface of thermally conductive chip 29).
Allowable Subject Matter
Claims 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 14, the prior art of record fails to disclose wherein the electronic component is first disposed on the first side of the circuit structure via a plurality of conductive bumps, and then the plurality of conductive pillars are disposed on the first side of the circuit structure to electrically connect the circuit layer, and at the same time, the thermally conductive chip is bonded onto the electronic component. Specifically, the prior art fails to disclose the specific sequence of the electronic component first being disposed on the first side of the circuit structure, and the plurality of conductive pillars and thermally conductive chip being subsequently bonded to the circuit layer and electronic component respectively.
For this reason, claims 15 and 16 would also be allowable if claim 14 were rewritten in independent form.
Response to Arguments
Applicant’s arguments, see pgs. 5-6, filed 7/28/2026, with respect to the rejection(s) of claim(s) 1 and 11 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of the prior art.
Applicant argued that Chang does not disclose the thermally conductive chip having a plurality of conductive vias penetrating through the thermally conductive chip. However, in a new interpretation of Chang, a first portion of the conductive layer in redistribution layer 201 can reasonably be interpreted as conductive vias and are shown penetrating through the thermally conductive chip. Examiner believes this interpretation to be within the broadest reasonable interpretation of the claims as written.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.J.S./Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
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