DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 7/1/2026. Claims 1-8 are pending in this application. Claims 1-3 and 6-7 are amended.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Vukkadala et al. (US 2016/0372353; hereinafter ‘Vukkadala’).
Regarding claim 1, Vukkadala teaches a method (1000, FIG. 10, [0087-0088]), comprising:
receiving a first location at which one or more first semiconductor elements are to be formed on a first wafer (1002, acquiring wafer shape values at a plurality of points corresponding to respective positions across the wafer at which processing is performed, and positions of a plurality of pattern features 956 formed on the wafer, wherein pattern features 956 correspond to patterned structures formed on the wafer during semiconductor fabrication process, FIG. 9B, [0081]);
measuring the first wafer to identify a first bow measurement of the first wafer (1004, generating a wafer shape change value at each of the plurality of points utilizing wafer shape values at different process levels);
calculating a second location that is shifted from the first location based on the first bow measurement (1006, generating one or more residual slope shape change metrics based on the wafer shape change values representing wafer bow process levels [0005], wherein positional deviations across the wafer, including those associated with pattern features 956, are determined based on the wafer bow, and wherein original positions of pattern features 956 correspond to the first location, and adjusted positions based on the positional deviations correspond to the second location); and
forming the one or more first semiconductor elements on the first wafer at the second location (1008, providing process control to one or more process tools, including film deposition, based on the generated slope shape change metrics to adjust processing across the wafer (FIG. 10, [0088]), wherein the process control adjusts processing conditions at positions across the wafer corresponding to the determined positional deviations, and wherein patterned features 956 are formed on the wafer (FIG. 9B, [0081]) correspond to structures formed during semiconductor fabrication processes [0004], such that processing at the adjusted positions results in formation of semiconductor elements at the second location).
Vukkadala does not explicitly teach the pattern features 956 as semiconductor elements.
Vukkadala, however, is directed to semiconductor fabrication processes in which patterned structures formed on a wafer are used to form semiconductor devices [0004], and further describes patterned features on a wafer, where positions of the patterned features 956 are controlled, and misalignment of the patterned features results in overlay error between patterned layers [0007-0008].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to recognize that the pattern features 956 of Vukkadala correspond to semiconductor elements as claimed, because the pattern features represent structures, and the placement of those structures directly affects alignment between patterned layers, which is characteristic of semiconductor elements formed and integrated during device fabrication [0004].
Regarding claim 4, Vukkadala teaches the method of claim 1, wherein calculating the second location that is shifted from the first location based on the first bow measurement includes calculating the second location that is shifted from the first location based on the first bow measurement and a thickness of the first wafer (determining a set of pattern placement error (PEE) residual value for each wafer, the PPE residual value for each point being a product of at least the residual slope shape metric for the point and a thickness of the wafer [0011], wherein PPE residual is expressed as a function including wafer thickness together with slope-based wafer shape characteristics (FIGS. 9A and 9B, [0082-0084]), where the residual slope shape metric is based on wafer shape characteristics including bow, and wherein original positions of the pattern features 956 correspond to the first location while adjusted positions based on the calculated positional deviations correspond to the second location).
Claims 2-3 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Vukkadala (US 2016/0372353) in view of Liu et al. (US 8802538; hereinafter ‘Liu’).
Regarding claim 2, Vukkadala teaches the method of claim 1, further comprising:
receiving a third location at which one or more second semiconductor elements are to be formed on a second wafer (1002, acquiring wafer shape values at a plurality of points corresponding to respective positions across a wafer at which processing is performed (FIG. 10, [0088]), wherein a plurality of wafers are received and wafer shape values are acquired for each wafer at a plurality of points [0011], indicating that the disclosed method is applicable to multiple wafers, including a second wafer; see also positions associated with a plurality of pattern features 956 formed on the wafer, FIG. 9B, [0081]);
measuring the second wafer to identify a second bow measurement of the second wafer (1004, generating a wafer shape change value at each of the plurality of points utilizing wafer shape values at different process levels and generating residual slope shape metrics for each wafer based on wafer shape values, [0011]);
calculating a fourth location that is shifted from the third location based on the second bow measurement (1006, generating one or more residual slope shape change metrics based on the wafer shape change values, wherein positional deviations across the wafer, including those associated with pattern features 956, are determined based on wafer shape characteristics and determining pattern placement error (PEE) values for each wafer based on wafer shape metrics, [0011]); and
forming the one or more second semiconductor elements on the second wafer at the fourth location (1008, providing process control to one or more process tools, including film deposition, based on the generated slope shape change metrics to adjust processing across the wafer, wherein the process control modifies pattern placement during processing such that semiconductor elements are formed at adjusted locations across the wafer).
Vukkadala does not teach the method further comprising bonding the one or more first semiconductor elements to the one or more second semiconductor elements.
Liu teaches a method further comprising bonding the one or more first semiconductor elements to the one or more second semiconductor elements (aligning bonding faces of two semiconductor wafers in a face-to-face relation, physically contacting the bonding faces, and annealing the wafers such that bonding occurs between respective metal pad layers, FIGS. 5 and 6, col. 7, line 66 – col. 8, line 6).
As taught by Liu, one of ordinary skill in the art would utilize and modify the above teaching into Vukkadala to obtain and achieve the method further comprising bonding the one or more first semiconductor elements to the one or more second semiconductor elements as claimed, because wafer bonding is a well-known technique for integrating semiconductor structures formed on separate substrates into a single device, such as 3D integrated circuit structure, and bonding between metal pad layers electrically and physically connects corresponding semiconductor structures (col. 1, lines 25-31).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Liu in combination with Vukkadala due to above reason.
Regarding claim 3, Vukkadala teaches the method of claim 1, further comprising:
providing a second wafer having one or more second semiconductor elements formed thereon (receiving a plurality of wafers and acquiring wafer shape values for each wafer at a plurality of points, [0011], and positions associated with a plurality of pattern features 956 formed on each wafer, FIG. 9B, [0081]);
measuring the second wafer to identify a second bow measurement of the second wafer (generating wafer shape change values and residual slope metrics for each wafer based on wafer shape values, FIG. 10, [0011, 0088]); and
wherein calculating the second location that is shifted from the first location based on the first bow measurement includes calculating the second location that is shifted from the first location based on the first bow measurement and the second bow measurement (determining PPE values for each wafer based on wafer shape characteristics, including residual slope shape metrics and wafer thickness, [0011], wherein wafer shape information from multiple wafers is utilizing in determining positional deviations across wafers).
Vukkadala does not teach the method further comprising bonding the one or more first semiconductor elements to the one or more second semiconductor elements.
Liu teaches a method further comprising bonding the one or more first semiconductor elements to the one or more second semiconductor elements (aligning bonding faces of two semiconductor wafers in a face-to-face relation, physically contacting the bonding faces, and annealing the wafers such that bonding occurs between respective metal pad layers, FIGS. 5 and 6, col. 7, line 66 – col. 8, line 6).
As taught by Liu, one of ordinary skill in the art would utilize and modify the above teaching into Vukkadala to obtain and achieve the method further comprising bonding the one or more first semiconductor elements to the one or more second semiconductor elements as claimed, because wafer bonding is a well-known technique for integrating semiconductor structures formed on separate substrates into a single device, such as 3D integrated circuit structure, and bonding between metal pad layers electrically and physically connects corresponding semiconductor structures (col. 1, lines 25-31).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Liu in combination with Vukkadala due to above reason.
Regarding claim 7, Vukkadala teaches the method of claim 1, further comprising: providing a second wafer having one or more second semiconductor elements formed thereon (providing a wafer having pattern features 956 formed thereon, FIG. 9B, [0081]).
Vukkadala does not teach the method further comprising bonding the one or more first semiconductor elements to the one or more second semiconductor elements.
Liu teaches a method further comprising bonding the one or more first semiconductor elements to the one or more second semiconductor elements (aligning bonding faces of two semiconductor wafers in a face-to-face relation, physically contacting the bonding faces, and annealing the wafers such that bonding occurs between respective metal pad layers, FIGS. 5 and 6, col. 7, line 66 – col. 8, line 6).
As taught by Liu, one of ordinary skill in the art would utilize and modify the above teaching into Vukkadala to obtain and achieve the method further comprising bonding the first semiconductor elements to the second semiconductor elements as claimed, because wafer bonding is a well-known technique for integrating semiconductor structures formed on separate substrates into a single device, such as 3D integrated circuit structure, and bonding between metal pad layers electrically and physically connects corresponding semiconductor structures (col. 1, lines 25-31).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Liu in combination with Vukkadala due to above reason.
Regarding claim 8, Vukkadala teaches the method of claim 1, but does not teach the method wherein the first semiconductor elements include bonding pads.
Liu teaches a method wherein the first semiconductor elements include bonding pads (metal pads 205 and 305 formed on bonding faces of semiconductor wafers, FIGS. 2A and 2B 6, col. 4, lines 18 and 24-25).
As taught by Liu, one of ordinary skill in the art would utilize and modify the above teaching into Vukkadala to obtain and achieve the method wherein the first semiconductor elements include bonding pads as claimed, because bonding (e.g., metal pads) are well-known structures used to electrically connect semiconductor elements between wafers (col. 2, lines 37-39).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Liu in combination with Vukkadala due to above reason.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Vukkadala (US 2016/0372353) in view of Sumiyoshi (US 2017/0060000).
Regarding claim 5, Vukkadala teaches the method of claim 1, but does not teach the method wherein calculating the second location that is shifted from the first location based on the first bow measurement includes calculating the second location that is shifted from the first location based on the first bow measurement and a radius of the first wafer.
Sumiyoshi teaches a method (FIG. 6, [0042]) wherein calculating the second location that is shifted from the first location based on the first bow measurement includes calculating the second location that is shifted from the first location based on the first bow measurement and a radius of the first wafer (expressing wafer positions using a coordinate system defined from a wafer center and normalized by a wafer radius [0066-0067], and calculating positional deviation amounts Δr and Δθ based on wafer shape (warping) characteristics [0071-0072], wherein positions defined by (r, θ) correspond to first locations and adjusted positions (r+Δr, θ+Δθ) correspond to second locations).
As taught by Sumiyoshi, one of ordinary skill in the art would utilize and modify the above teaching into Vukkadala to obtain and achieve the method wherein calculating the second location that is shifted from the first location based on the first bow measurement includes calculating the second location that is shifted from the first location based on the first bow measurement and a radius of the first wafer as claimed, because incorporating radius-based coordinate modeling is useful for improving accuracy in determining positional deviations across an entire wafer surface form a center to an edge [0066-0067].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Sumiyoshi in combination with Vukkadala due to above reason.
Regarding claim 6, Vukkadala teaches the method of claim 1, wherein calculating the second location that is shifted from the first location based on the first bow measurement includes calculating the second location that is shifted from the first location based on the first bow measurement, a thickness of the first wafer, a distance between any neighboring two of the one or more first semiconductor elements (determining a set of PPE residual values for each wafer, the PPE residual value for each point being a product of at least the residual slope shape metric for the point and a thickness of the wafer [0011], wherein PPE residual is expressed as a function including wafer thickness together with slope-based on wafer shape characteristics (FIGS. 9A and 9B, [0082-0084]), and wherein the residual slope shape metric is based on wafer shape characteristics including bow, and wherein distances between any neighboring two of the first semiconductor elements correspond to distances between adjacent pattern features 956 on the wafer, and original positions of the pattern features 956 correspond to the first location while adjusted positions based on the calculated positional deviations correspond to the second location).
Vukkadala does not teach the method wherein calculating the second location based on a radius of the first wafer.
Sumiyoshi teaches the method wherein calculating the second location based on a radius of the first wafer (expressing wafer positions using a coordinate system defined from a wafer center and normalized by a wafer radius [0066-0067], and calculating positional deviation amounts Δr and Δθ using (r, θ) coordinates [0071-0072], wherein positions defined by (r, θ) correspond to first locations and adjusted positions (r+Δr, θ+Δθ) correspond to second locations).
As taught by Sumiyoshi, one of ordinary skill in the art would utilize and modify the above teaching into Vukkadala to obtain and achieve the method wherein calculating the second location based on a radius of the first wafer as claimed, because incorporating radius-based coordinate modeling is useful for improving accuracy in determining positional deviations across an entire wafer surface form a center to an edge [0066-0067].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Sumiyoshi in combination with Vukkadala due to above reason.
Response to Arguments
Applicant's arguments filed on 7/1/2026 have been fully considered but they are not persuasive.
Applicant submits, in page 6 of Remark, that
“Vukkadala discloses generating wafer geometry metrics for purposes such as wafer characterization, wafer sorting, overlay monitoring, and process control”.
The examiner respectfully disagrees.
Vukkadala is not limited to merely generating wafer geometry metrics. Vukkadala teaches that wafer-shape changes cause in-plane distortion and pattern-placement errors. Vukkadala further teaches calculating wafer-level or field-level process-tool correctable based on measured wafer shape. The correctable expressly include X- and Y-direction positional shifts and are provided to a lithography scanner to correct a subsequently formed pattern [0038, 0046-0049, 0063-0065].
Accordingly, the nominal position of a pattern corresponds to the claimed first location, and the position resulting from application of the calculated X- and Y-direction shifts corresponds to the claimed second location. Applying the calculated positional correctable to the scanner causes the patterned semiconductor elements to be formed at the corrected second location. Claim 1 does not require physical relocation and already formed elements or require any particular manner of expressing or storing the first and second locations. Therefore, Applicant’s general assertion that Vukkadala does not disclose or suggest forming the semiconductor elements at the claimed shifted location does not address the cited teachings and does not overcome the rejection.
Applicant further submits, in page 6 of Remark, that
“Applicant notes that the Office Action additionally equates Vukkadala's pattern features 956 with the claimed semiconductor elements. Even assuming arguendo that pattern features 956 could be considered semiconductor elements, such a finding does not remedy the deficiencies discussed above”.
The examiner respectfully disagrees.
Claim 1 does not limit the term “semiconductor elements” to elements made of semiconductor material or to completed semiconductor devices. Rather, Applicant’s Specification expressly describes semiconductor elements as including “different materials and structural formations” and “lithographic patterns such as bonding pads” [0021, 0029].
Vukkadala similarly teaches that layers formed on a semiconductor wafer may include repeatable patterned features whose formation and processing ultimately result in completed semiconductor device [0036]. Vukkadala’s patter features 956, which are disposed on a pattern surface of the wafer and are subject to pattern placement errors caused by changes in wafer shape, therefore reasonably correspond to the claimed semiconductor elements (FIG. 9B, [0081]). Moreover, as discussed above, Vukkadala teaches calculating positional corrections based on measured wafer shape and applying those corrections to a subsequently formed pattern. Accordingly, Applicant’s arguments are not persuasive.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure in that Lin et al. (US 2014/0356983), Trezza (US 2008/0197488), and Liu et al. (US 2011/0248396) teach compensating for wafer bow or distortion to improve semiconductor wafer bonding and alignment.
THIS ACTION IS MADE FINAL. Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for replying to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/25/26
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