DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 07/26/2026 have been fully considered but they are not persuasive.
Applicant argues that prior art of record Stefanov does not teach the independent claims as written.
The applicant argues in part;
The sensing nodes of Stefanov are formed in a light-sensitive area of a silicon layer of the imaging device and/or are included in the pixels of the imaging device. The examiner agrees that this is one possible interpretation under broadest reasonable interpretation, however the applicant does not claim that any sensing node is not included in a pixel region of the imaging device, Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The examiner recommends further defining the structure of the sensing node within the claims.
“source region 113 cannot be a source region for a VCVFD structure as presently claimed since it is the source of source follower transistor 119”. The examiner respectfully disagrees as the applicant does not claim the VCVFD does not include a source follower transistor and/or gate structure, although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The examiner recommends further defining the structure of the VCVFD within the claims.
“P-well 107 cannot act as a channel region for a VCVFD structure” as “p-well” of Stefanov is configured and used a substrate doping for the reset transistor and source follower/gate electrode. The examiner respectfully disagrees, the examiner as written in the prior rejection and this rejection does not match the channel region included in the VCVFD structure as the entirety of P-well 107, as rejected the examiner matched the channel region to P-well under RG1/117 and/or 119, fig. 16, the p-well forms a clear NPN transistor structure wherein the P-well is the channel for the N+ source/drain regions and gates 117 and 119. In addition, the applicant does not claim that the channel as claimed is not formed from a doped substrate. The examiner recommends further defining the structure of the VCVFD within the claims.
“the RG/gate electrode 117” of Stefanov cannot act as a second gate configured to control a variable capacitance via voltage applied to it”. While the Applicant makes some very good points about the differences in functionality and/or operation/use of a reset gate vs a VCVFD structure it is still unclear to the examiner what the implied structural and material difference is, if any, as the claims are written without importing additional limitations from the specification. Although the examiner does consider the functionality and/or operation/use of a device, for device patents the functionality and/or operation/use of a device is only considered so far as the implied structure and/or composition [See MPEP 2112.01]. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
The applicant repeats these arguments for the dependent claims. stating that the combination of Meynants and Chuang do not overcome the deficiencies of Stefanov. This is not persuasive, as discussed above the examiner does not see any deficiencies of Stefanov regarding the argued elements of the claimed structure and device.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-11, 14-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20210217799 A1 Stefanov hereafter “Stefanov”.
Claim 1 Stefanov teaches an image sensor, comprising: a silicon layer (203 fig. 16, Sufficiently disclosed as “monocrystalline epitaxial silicon” paragraph 0083 when interpreted in view of fig. 16) configured to generate electron-hole pairs [This functional limitation is met in view of MPEP 2112.01 as the structure and/or composition is the same as disclosed and/or claimed] when light is incident on a light- sensitive area of the silicon layer (Pinned Photodiode 207 fig. 16);
Circuits [sufficiently illustrated fig. 16] formed on a first side (topside fig. 16) of the silicon layer, wherein the circuits comprise a channel (Buried channel 1303 contacting 105 and 213 and/or TG and SG fig. 16) and first gate electrodes (comprising at least 105 and 213 and 215 fig. 16) configured to control electron accumulation in the channel in response to generation of the electron-hole pairs [this functional limitation is met in view of MPEP 2112.01 as the structure is the same as disclosed and/or claimed]; and
a sensing node (sense node fig. 16) electrically connected to the circuits [sufficiently illustrated fig. 16], formed on the first side of the silicon layer adjacent to the circuits and outside of the light-sensitive area [sufficiently illustrated fig. 16], and formed by a Voltage-Controlled Variable Floating Diffusion (VCVFD) structure [sufficiently illustrated fig. 16], wherein the VCVFD structure comprises:
a source region (103 and 113 fig. 16) and a channel region (P-well under RG1/117 and/or 119, fig. 16 under broadest reasonable interpretation), wherein the source region of the VCVFD structure is connected to the channel of the circuits and an output circuit of the image sensor [met under broadest reasonable interpretation sufficiently illustrated fig. 16, also illustrated fig. 18 see annotation below for connection to the output circuit.]; and
a second gate electrode (117 fig. 16, and further illustrated fig. 18) adjacent to the source region and configured to control a variable capacitance of the VCVFD structure via voltage applied to the second gate electrode [this functional limitation is met under MPEP 2112.01 the structure and/or composition is the same as disclosed and/or claimed] by an electrical connection (RG1 illustrated fig. 16, and further illustrated fig. 18) to the second gate electrode [this functional limitation is met under MPEP 2112.01 the structure and/or composition is the same as disclosed and/or claimed],
wherein the VCVFD structure is configured to convert a charge responsive to the electron accumulation to a voltage proportional to an amount of the charge and dependent on the variable capacitance [this functional limitation is met under MPEP 2112.01 the structure and/or composition is the same as disclosed and/or claimed, and/or alternatively disclosed with sufficient specificity paragraph 0018 “the circuitry defining the first path is circuitry configured to produce a signal representative of the charge generated in the pinned photodiode via capacitive coupling to charge in the substrate”], and
wherein the output circuit is configured to generate output responsive to the voltage output by the VCVFD structure [this functional limitation is met under MPEP 2112.01 the structure and/or composition is the same as disclosed and/or claimed, and/or alternatively disclosed with sufficient specificity paragraph 0018 “a sense gate electrode formed on the substrate and capacitively coupled to charge in the imaging device; and circuitry configured to measure the voltage change of the sense gate”].
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Stefanov annotated Fig. 18: highlighting the output circuit
Claim 2 Stefanov teaches as shown above the sensor of claim 1, wherein the image sensor is configured as a charge-coupled device [met under broadest reasonable interpretation in view of “capacitive coupling” and/or “pinned photodiode” paragraph 0018, and/or alternatively met under MPEP 2112.01 as the structure and/or composition is the same as claimed and/or disclosed].
Claim 3 Stefanov teaches as shown above the sensor of claim 1, wherein the image sensor is configured as a backside illuminated charge-coupled device [sufficiently disclosed paragraph 0068 “backside illuminated image sensors” this functional/property limitation is met under MPEP 2112.01 as the structure and/or composition is the same as claimed and/or disclosed in this case, the structure of fig. 16 matches the structure of fig. 4 of the instant application ].
Claim 4 Stefanov teaches as shown above the sensor of claim 1, wherein the image sensor is configured as a charge-coupled device configured to function as a time-delay integration sensor [met under broadest reasonable a time-delay and/or time interval under broadest reasonable interpretation is sufficiently illustrated fig. 15 and “capacitive coupling” paragraph 0018, and/or this functional/property limitation is met under MPEP 2112.01 as the structure and/or composition is the same as claimed and/or disclosed in this case, the structure of fig. 16 matches the structure of fig. 4 of the instant application].
Claim 5 Stefanov teaches as shown above the sensor of claim 1, wherein the circuits are configured as charge-coupled device circuits [met under broadest reasonable interpretation in view of “capacitive coupling” paragraph 0018, and/or alternatively met under MPEP 2112.01 as the structure and/or composition is the same as claimed and/or disclosed].
Claim 6 Stefanov teaches as shown above the sensor of claim 1, wherein the circuits are configured as metal-oxide- semiconductor field-effect transistors (MOSFETs) [sufficiently disclosed in paragraph 0074 “CMOS” under broadest reasonable interpretation].
Claim 7 Stefanov teaches as shown above the sensor of claim 1, wherein the silicon layer is a silicon epitaxial layer [sufficiently disclosed paragraph 0083 “monocrystalline epitaxial silicon” in view of fig. 16].
Claim 9 Stefanov teaches as shown above the sensor of claim 1, wherein the channel of the circuits comprises an n-type doped buried channel [sufficiently illustrated fig. 16 “n” and “buried channel”].
Claim 10 Stefanov teaches as shown above the sensor of claim 1,
wherein the source region of the VCVFD structure has a dopant concentration equal to or higher than a dopant concentration in the channel of the circuits [sufficiently illustrated fig. 16 as “n” and “n+”] wherein the source region of the VCVFD structure and the channel of the circuits are doped with the same polarity[met under broadest reasonable interpretation fig. 16 buried channel adjacent to TG and SG is “n” and buried channel adjacent to IG is “n”].
Claim 11 Stefanov teaches as shown above the sensor of claim 1, wherein the source region of the VCVFD structure is further connected to a charge reset structure in the image sensor [sufficiently illustrated fig. 16 reset gate “RG1”, and further illustrated fig. 18 with reset gates “RG1” and “RG2”].
Claim 14 Stefanov teaches the sensor of claim 1, wherein the image sensor further comprises an antireflection layer (205 substate (P++) fig. 16 met under MPEP 2112.01 the composition is the same as disclosed, disclosed as “boron P+ regions” paragraph 0067 in conjunction with fig. 16 wherein boron is the p-type dopant used to achieve P++ and/or alternatively disclosed as “aluminum oxide” to achieve P++ implant layer Paragraph 0068 in view of fig. 16) disposed on a second side of the silicon layer opposite to the first side [].
Claim 15 Stefanov teaches as shown above the sensor of claim 1, wherein the circuits are configured as a two-dimensional array of pixels [sufficiently illustrated fig. 8 “Pixel array MxN”].
Claim 16 Stefanov teaches the sensor of claim 1, wherein the circuits are configured as multiple columns of pixels comprising at least first and second columns of pixels [sufficiently illustrated by fig. 8 “pixel array” and “N columns”], wherein the at least first and second columns of pixels comprise one or more pixels [sufficiently illustrated by fig. 8 “pixel array” and “M rows”], wherein the sensing node is one of multiple sensing nodes in the image sensor [sufficiently illustrated by the pixel illustrated fig. 11 and fig. 16 in view of fig. 8], wherein the multiple sensing nodes comprise at least first and second sensing nodes [sufficiently illustrated by the pixel illustrated fig. 11 and fig. 16 in view of fig. 8], and wherein the first and second sensing nodes are electrically connected to all of the one or more pixels in the first and second columns of pixels, respectively[sufficiently illustrated by the pixel illustrated fig. 11 and fig. 16 in view of fig. 8].
Claim 17 Stefanov teaches as shown above the sensor of claim 1, wherein the circuits are configured as multiple columns of pixels comprising at least first and second columns of pixels [sufficiently illustrated by fig. 8 “pixel array” and “N columns”], wherein the at least first and second columns of pixels comprise one or more pixels [sufficiently illustrated by fig. 8 “pixel array” and “M rows”], and wherein the sensing node is electrically connected to the one or more pixels in the first and second columns of pixels [sufficiently illustrated by the pixel illustrated fig. 11 and fig. 16 in view of fig. 8].
Claim 18 Stefanov teaches as shown above the sensor of claim 1, wherein the channel region of the VCVFD structure is configured as an n-type buried channel [sufficiently illustrated fig. 16 “n” “buried channel”].
Claim 19 Stefanov teaches as shown the sensor of claim 1, wherein the channel region of the VCVFD structure is configured as an n-type surface channel [the structure of the “surface channel” 404 within 450 as claimed and illustrated in fig. 4 matches that of the structure of “buried channel” 404 outside 450 within fig. 4 as claimed Gate electrode (452/440, ect) -> gate dielectric (408) -> channel (404) buried in and at a surface of the substrate -> substrate, prior art similarly shows gate electrode (RG/117 and/or 119)->gate dielectric (gate oxide/209)-> channel ( “pixel p-well”) buried in and at a surface of the substrate -> substrate (203 p-type epitaxial layer). If the applicant intended to imply the structure of ~the channel being at a surface of the substrate~ the limitation is met under broadest reasonable interpretation, if the applicant intend for “surface channel” to imply a function/property of the channel such as the depth of the channel from surface when in the transistor is in a “ON” state, the limitation is met under MPEP 2112.01. if the applicant intends for the limitation “surface channel” to imply a structure other than ~the channel is at a surface of the substrate~ that would differentiate it from the “buried channel” the examiner recommends explicitly claiming such structure and to point out said structural difference within the drawings for clarity].
Claim 20 Stefanov teaches as shown above the sensor of claim 1, wherein the VCVFD structure further comprises a drain region (109 and/or 111 fig. 16) connected to the channel region of the VCVFD structure, and wherein the source region and the drain region of the VCVFD structure are electrically connected [sufficiently illustrated fig. 16 (source (103)-> channel (pixel p-well) -> drain (RD1/109)].
Claim 21 Stefanov teaches as shown above the sensor of claim 1, wherein the circuits are configured as pixels comprising at least first and second pixels (sufficiently illustrated by pixel array fig. 8), wherein the sensing node is electrically connected to the first and second pixels (sufficiently illustrated fig. 11 and 16 in view of fig. 8), and wherein the image sensor or a computer subsystem is configured to calibrate the sensing node thereby calibrating the first and second pixels (met under MPEP 2112.01 the structure as disclosed is the structurally and/or compositionally the same as claimed and/or disclosed).
Claim 22 Stefenov teaches as shown above the sensor of claim 1, wherein the image sensor is positioned in an inspection system [Met under MPEP 2112.01, the structure and/or composition is the same as disclosed, thus the functional limitation of being position in an inspection system is met as the sensor qualifies as an inspection system in and of itself and/or alternatively met under broadest reasonable interpretation an “image sensor” and/or “machine vision” system, paragraph 0002, qualifies as an inspection system that inspects and/or senses image based data] so that the light incident on the light-sensitive area is light from a specimen being inspected by the inspection system, and wherein the inspection system is configured for detecting defects on the specimen based on the output generated by the output circuit of the image sensor [met under MPEP 2114 “Manner of operating the device does not differentiate apparatus claim from the prior art” if the prior art apparatus teaches all the structural limitations of the claim].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Stefanov as applied to the claims above, and further in view of US 20140231879 A1 Meynants et al hereafter “Meynants”.
Claim 8 Stefanov teaches as shown above the sensor of claim 1, wherein the silicon layer is a silicon epitaxial layer [sufficiently disclosed Paragraph 0083 “monocrystalline epitaxial silicon”], and wherein the silicon epitaxial layer comprises intrinsic or p-type doped silicon [fig. 16 “P-type epitaxial layer”]; and a P-well dopant concentration of around 1017 cm-3 [Paragraph 0084 “The p-well is normally 1 μm deep and has doping concentration of around 1017 cm-3”]
Stefanov does not explicitly teach the silicon epitaxial layer with a dopant concentration less than 1014 cm-3.
Meynants teaches pinned photodiode imaging device [Fig. 2] comprising a P-well (p-well fig. 2) with a dopant concentration of 1017cm-3 [1E17/cm3 Paragraph 0007], and a p-type epitaxial layer (p-epi fig. 2) with a dopant concentration of 5x1014cm-3 [5e14/cm3 Paragraph 0007] and that the difference in concentrations creates a potential barrier [Paragraph 0007, “
φ
=
K
T
q
l
n
(
N
a
+
N
a
)
”]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Stefanov in view of Meynants such that the silicon epitaxial layer with “a dopant concentration less than 1014 cm-3” as part of routine optimization of the result effected variable of potential difference between the epitaxial layer and the p-well [See MPEP 2144.05 II.] and/or to achieve a specific potential barrier between the epitaxial layer and the p-well.
Claim 12 Stefanov teaches as shown above the sensor of claim 1, wherein
Stefanov does not teach the channel region of the VCVFD structure and the channel of the circuits are doped with the same polarity.
Meynants teaches a similar device comprising a channel region (p-well under RST fig. 2) of a VCVFD structure [sufficiently illustrated fig. 2 and/or met under MPEP 2112.01 as the structure and/or composition is the same] and a channel (P-well under Ø1, Ø2, Ø3 fig. 2) of circuits [comprising Ø1, Ø2, Ø3 fig. 2] are doped with a same polarity [sufficiently illustrated fig. 2 as p-type polarity].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Stefanov in view of the device of Meynants to select the same doped material for the channel of the circuits and for the channel region of the VCVFD structure such that they “doped with a same polarity” as selection of a known material based on its suitability for its intended use is prima facie type obviousness [See MPEP 2144.07] and/or to achieve the same and/or a similar potential barrier and/or work function between the channels and the source region of the sense node [see Meynants paragraph 0007 sufficiently discloses that dopant concentrations of adjacent layers effects the potential difference between them and/or at their interface.].
Claim 13 Stefanov teaches as shown above the sensor of claim 1, wherein the silicon layer is a silicon epitaxial layer [Paragraph 0083 “Monocrystalline epitaxial silicon” in view of fig. 17 ], wherein the image sensor further comprises a thin p-type layer (205 Substrate (P++)) with a dopant concentration higher than a dopant concentration of the silicon epitaxial layer (fig. 16 sufficiently disclosed P++ vs P-type), and wherein the thin p-type layer is disposed on a second side [bottom side fig. 16] of the silicon epitaxial layer opposite to the first side.
Stefanov does not explicitly teach the dopant concentration “at least ten times higher”
Meynants teaches and similar device [fig. 2] and that that a difference in dopant concentrations creates a potential barrier wherein the potential difference is for P-type dopants is “
φ
=
K
T
q
l
n
(
N
a
+
N
a
)
” [sufficiently disclosed paragraph 0007].
It would have been obvious to one of ordinary skill in the art to modify Stefanov in view of Meynants such that the dopant concentration “at least ten times higher” to achieve a suitably large potential barrier and/or as a part of routine optimization of the potential difference between the layers [MPEP 2144.05 II.].
Claims 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Stefanov as applied to the claims above, and further in view of US 20160315114 A1 Chuang et al hereafter “Chuang”
Claim 23 Stefanov teaches a system (fig. 8) configured for determining information for a specimen (this limitation is met under broadest reasonable interpretation of “imaging device” which determines image-based data in combination with the applications of “automotive imaging” and “surveillance” wherein the specimen maybe automobiles and/or pedestrians, and/or “spectroscopy” wherein the specimen maybe a material and/or chemical compound, alternatively the limitation is met under MPEP 2112.01 the structure has all the required structure as disclosed to perform the function of determining information for a specimen), comprising;
an image sensor (fig. 8 wherein fig. 16 is a ) positioned in a path of light from the specimen [MPEP 2114 Manner of operating the device does not differentiate apparatus claim from the prior art, an image sensor must necessarily be in a path of light and/or directed at the object/specimen to collect image based-data from the specimen] and comprising: a silicon layer (203 P-type epitaxial layer fig. 16) configured to generate electron-hole pairs when the light from the specimen is incident on a light-sensitive area (Pinned photodiode fig. 16) of the silicon layer [this functional limitation is met under MPEP 2112.01 as the structure is the same as disclosed and/or claimed];
circuits (comprising but not limited to 105/TG and/or 213/SG and/or 215/IG fig. 16 also illustrated fig. 18) formed on a first side (top side fig. 16) of the silicon layer, wherein the circuits comprise a channel (1303 buried channel fig. 16) and first gate electrodes (105, and/or 213, and/or 215 fig. 16) configured to control electron accumulation in the channel in response to generation of the electron-hole pairs [met under MPEP 2112.01 the structure is the same as disclosed and/or claimed]; and
a sensing node (Sense node fig. 16) electrically connected to the circuits [sufficiently illustrated as being electrically connected fig. 16], formed on the first side of the silicon layer adjacent to the circuits and outside of the light-sensitive area [sufficiently illustrated fig. 16 “sense node” region does not overlap with “pinned photodiode” region],
and formed by a Voltage-Controlled Variable Floating Diffusion (VCVFD) structure [met under MPEP 2112.01 the structure is the same as disclosed and/or claimed], wherein the VCVFD structure comprises:
a source region (103 fig. 16) and a channel region (Pixel p-well fig. 16), wherein the source region of the VCVFD structure is connected to the channel of the circuits [sufficiently illustrated fig. 16] and an output circuit of the image sensor [sufficiently illustrated fig. 16 and fig. 18, see annotation below for output circuit]; and
a second gate (117 fig. 16) electrode adjacent to the source region and configured to control a variable capacitance of the VCVFD structure via voltage applied to the second gate electrode by an electrical connection (RG1 fig. 16) to the second gate electrode [met under MPEP 2112.01 the structure and/or composition is the same as disclosed and/or claimed],
wherein the VCVFD structure is configured to convert a charge responsive to the electron accumulation to a voltage proportional to an amount of the charge and dependent on the variable capacitance [met under MPEP 2112.01], and
wherein the output circuit is configured to generate output responsive to the voltage output by the VCVFD structure [sufficiently illustrated fig. 18 and/or met under MPEP 2112.01 as]; and
a computer subsystem (comprising 809, 811, and 813 fig. 8 met under broadest reasonable interpretation wherein processing module, signal processing and arbitration module constitute computer subsystems) configured for determining information for the specimen based on the output [sufficiently illustrated fig. 8 they determine and/or “process” and/or “arbitrate” information from the pixel array in the form of sensor outputs and/or met under MPEP 2112.01 the structure is the same as disclosed and/or claimed].
Stefanov does not teach: an illumination subsystem configured for directing light generated by a light source to a specimen.
Chuang teaches a system (fig. 1) configured for determining information for a specimen (Sample 108 fig. 1) [met under MPEP 2112.01 the structure and/or composition is the same as disclosed], comprising:
an illumination subsystem (comprising at least 102, 103, and 105 fig. 1) configured for directing light generated by a light source (102 fig. 1) to a specimen (108 fig. 1); an image sensor (106 fig. 1) positioned in a path of light from the specimen [sufficiently illustrated fig. 1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Stefanov in view of the apparatus of Chuang and/or to substitute the device of Stefanov for the detector of Chung such that there is “an illumination subsystem configured for directing light generated by a light source to a specimen” as combining equivalents known for the same purpose and/or substituting equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06] in this case it is combining a systems for imaging and/or substituting an sensor/detector for imaging with another sensor/detector for imaging.
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Stefanov Annotated fig. 18: highlighting the output circuit
Claim 24 Stefanov in view of Chuang teaches as shown above the system of claim 23, wherein the system is further configured as an inspection system, and wherein the information for the specimen comprises information for defects detected on the specimen based on the output [this functional limitation is met under MPEP 2112.01 as the composition and/or structure is the same as disclosed, and/or MPEP 2114 manner of operating the device does not differentiate apparatus claim from the prior art].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WCT/Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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