DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 18-20 and new claims 21-37 in the reply filed on 4/1/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 18, 20-22, 25-26, and 29-36 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KOKETSU (US 20090206411).
Regarding claim 18, KOKETSU discloses a method comprising:
forming, in an overlay mark region (the Alignment Mark Formation Region, see fig 18, para 125) of an integrated circuit (the device shown in fig 11-28), a first diffraction grating of first conductive structures (the diffraction pattern formed of P1b, see fig 18, para 125 and 82) with a first deposition process (the deposition process in fig 18, see para 125);
forming, in the overlay mark region with a second deposition process (the deposition process in fig 20, see para 128), a second diffraction grating of second conductive structures (the diffraction pattern of P1a, see fig 20, para 82 and 128) above and laterally offset from the first conductive structures (P1a is above and laterally offset from P1b, see fig 20),
wherein a respective plurality of the first conductive structures is positioned laterally between each pair of adjacent second conductive structures (there are a plurality of structures P1b laterally between each P1a, see fig 6);
forming, in a device region (the integrated circuit formation region, see fig 20), first metal connection structures (fig 20, L2, para 128) with the second deposition process (L2 is formed by the deposition process in fig 20 that also forms P1a, see fig 20, para 128); and
forming, in the device region with a third deposition process (the deposition process in fig 21, see para 129), second metal connection structures (fig 21, L3, para 131) in contact with the first metal connection structures (L3 is in contact with L2 by means of PLG3, see fig 21) with an alignment based on the first and second diffraction gratings (the upper layer including L3 is formed aligned with P1a and P1b, see fig 6 and 21, para 76 and 131).
Regarding claim 20, KOKETSU discloses the method of claim 18, comprising forming a shield grating of elongated structures below the second diffraction grating (the sides of GR1, see fig 5 and 18, para 125).
Regarding claim 21, KOKETSU discloses a method, comprising:
depositing, in an overlay mark region (the guard ring and alignment marker region, see fig 18) of an integrated circuit (the device in fig 11-28(, a shield grating of elongated structures (the sides of GR1, see fig 5 and 18, para 125);
depositing (by the disposition process in fig 18, see para 125), in the overlay mark region, a first diffraction grating of first conductive structures (fig 18, P1B, para 125) including a plurality of first groups of the first conductive structures (alternate columns of P1b between columns of P1a, see fig 6); and
depositing, in the overlay mark region, a second diffraction grating of second conductive structures (P1a, see fig 20, para 128) above the first diffraction grating of first conductive structures and the shield grating (P1a is above GR1 and P1b, see fig 20),
wherein a respective first group of the first conductive structures is positioned laterally between each pair of adjacent second conductive structures (a column of P1b is disposed between pairs of P1a, see fig 6).
Regarding claim 22, KOKETSU discloses the method of claim 21, wherein the elongated structures extend in a first direction (GR1 extends in the direction into the plane of fig 20, see fig 5 and 20),
wherein the first conductive structures and the second conductive structures extend in a second direction transverse to the first direction (P1a and P1b each have an extension in the horizontal direction in fig 20).
Regarding claim 25, KOKETSU discloses the method of claim 21, wherein the elongated structures, the first conductive structures of each first group, and the second conductive structures each extend in a first direction (each of GR1, P1b and P1a have an extension in the horizontal direction in fig 20).
Regarding claim 26, KOKETSU discloses the method of claim 25, wherein the first diffraction grating includes a plurality of second groups of the first conductive structures (the alternate columns of P1b between the columns of P1a and between the first groups, see fig 6 and 20) each extending in a second direction transverse to the first direction (each of the elements P1b have an extension in the direction perpendicular to the plane of fig 20, see fig 5, 6 and 20).
Regarding claim 29, KOKETSU discloses the method of claim 25, wherein the second conductive structures and the first conductive structures of the first groups each have a same length (P1a and P1b can both be 600 nm in size, see para 74 and 78).
Regarding claim 30, KOKETSU discloses the method of claim 21, wherein the first conductive structures and the elongated structures are positioned on a top surface of a substrate (GR1 and P1b are at least indirectly on the top surface of the substrate 1S, see fig 18, para 125).
Regarding claim 31, KOKETSU discloses the method of claim 21, comprising:
a first interlevel dielectric layer on the elongated structures (8 is on a bottom surface of GR1, see fig 18, 8, para 125), wherein the first conductive structures are on a top surface of the first interlevel dielectric layer (P1b are on a top surface of 8, see fig 18); and
a second interlevel dielectric layer on the first conductive structures (fig 19, 9, para 126), wherein the second conductive structures are on a top surface of the second interlevel dielectric layer (P1a is on a top surface of 9, see fig 20).
Regarding claim 32, KOKETSU discloses a method, comprising:
depositing a source/drain region of a transistor in a device region (the source/drain regions 6, see fig 15, para 118 deposited in the integrated circuit formation region); and
depositing a first metal connection structure (fig 17, PLG1, para 124) of a first material (Ti/TiN, see para 124) electrically coupled to the source/drain region (see fig 17);
depositing a first diffraction grating of first conductive structures (fig 18, P1B, para 125) in an overlay mark region (the Alignment Mark Formation Region, see fig 18); and
depositing a second diffraction grating of second conductive structures of the first material (P1a can also be Ti/TiN, see fig 20, para 128) above and offset from the first conductive structures (P1a are above and offset from P1b, see fig 20),
wherein a plurality of the first conductive structures is positioned laterally between each pair of adjacent second conductive structures (a column of P1b is disposed between pairs of P1a, see fig 6).
Regarding claim 33, KOKETSU discloses the method of claim 32, wherein the device region includes a second metal connection structure of a second material in contact with the first metal connection structure (L2 which can comprise Cu doped Al, see fig 20, para 128).
Regarding claim 34, KOKETSU discloses the method of claim 33, wherein the first metal connection structure is source/drain contact (PLG1 are source/drain contacts, see fig 17, para 124).
Regarding claim 35, KOKETSU discloses the method of claim 34, wherein the overlay mark region includes a shield grating of elongated structures below the second diffraction grating (the portions of 1S between isolation regions P3 which is below P1a, see fig 12, para 106 and fig 20).
Regarding claim 36, KOKETSU discloses the method of claim 35, wherein the elongated structures are semiconductor fins (the structures are portions of the semiconductor 1S between P3, see fig 12, para 106).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOKETSU (US 20090206411) in view of YEO (US 20010014531).
Regarding claim 19, KOKETSU discloses the method of claim 18.
KOKETSU fails to explicitly disclose a method, comprising aligning the third conductive structures with the second conductive structures with a diffraction-based overlay alignment process with the first and second diffraction gratings.
YEO teaches a method, comprising aligning the third conductive structures with the second conductive structures with a diffraction-based overlay alignment process with the first and second diffraction gratings (alignment can be done by using diffraction between different layers, see fig 6, para 45).
KOKETSU and YEO are analogous art because they both are directed towards method of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the emthod of KOKETSU with the diffraction-based alignment process of YEO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOKETSU with the diffraction-based alignment process of YEO in order to increase alignment accuracy (see YEO, para 47)
Claim(s) 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOKETSU (US 20090206411) in view of MINODA (US 20170329217).
Regarding claim 23, KOKETSU discloses the method of claim 22.
KOKETSU fails to explicitly disclose a method, wherein each first group includes first conductive structures of differing widths.
MINODA teaches a method, wherein each first group includes first conductive structures of differing widths (the widths of the diffraction grating patterns can decrease from one to the other, see fig 18, para 88).
KOKETSU and MINODA are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KOKETSU with the differing widths of MINODA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of KOKETSU with the differing widths of MINODA in order to improve accuracy (see MINODA para 88).
Regarding claim 24, KOKETSU discloses the method of claim 22.
KOKETSU fails to explicitly disclose a method, wherein each first group includes multiple different separation distances between adjacent pairs of the first conductive structures of the first group.
MINODA teaches a method, wherein each first group includes multiple different separation distances between adjacent pairs of the first conductive structures of the first group (the spacing between the patterns of the diffraction grating can increase from one to the other, see fig 18, para 88).
KOKETSU and MINODA are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KOKETSU with the differing spacings of MINODA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of KOKETSU with the differing spacings of MINODA in order to improve accuracy (see MINODA para 88).
Claim(s) 27-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOKETSU (US 20090206411) in view of PARK (US 9929104).
Regarding claim 27, KOKETSU discloses the method of claim 26.
KOKETSU fails to explicitly disclose a method, wherein the first conductive structure of the second groups each extend over multiple elongated structures.
PARK teaches a method, wherein the first conductive structure of the second groups each extend over multiple elongated structures (each of the lower patterns 110 extends over multiple elongated parts of 220, see fig 2, para 16).
KOKETSU and PARK are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KOKETSU with the structure configuration of PARK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of KOKETSU with the structure configuration of PARK in order to increase accuracy (see PARK para 51).
Regarding claim 28, KOKETSU and PARK disclose the method of claim 27.
KOKETSU further discloses a method, wherein each second group is positioned between two adjacent columns of first groups (the first and second groups are alternating columns of P1b, and so will be between each other.
Claim(s) 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOKETSU (US 20090206411) in view of KOKUBUN (US 20130093034).
Regarding claim 37, KOKETSU discloses the method of claim 36.
KOKETSU fails to explicitly disclose a method, wherein the first conductive structures are polysilicon.
KOKUBUN teaches a method, wherein the first conductive structures are polysilicon (the diffraction patterns 61 can be polysilicon, see fig 2A, para 50).
KOKETSU and KOKUBUN are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KOKETSU with the polysilicon of KOKUBUN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of KOKETSU with the polysilicon of KOKUBUN in order to use a material with the desired index of refraction (see KOKUBUN para 50).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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