Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1- are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. 20200006545 to Liu et al. (Liu) in view of U.S. Pat. Pub. No. 20220310840 to Li et al. (Li).
Regarding Claim 1, Liu teaches in Figs. 2+ at least, a method, comprising:
forming nanostructures 251 over a substrate 270;
forming a source/drain opening [0019] adjacent the stack of nanostructures;
forming a semiconductor layer 292 in the source/drain opening;
forming an amorphous semiconductor layer by performing an ion implantation 231 on the semiconductor layer [0030]; and
forming a recrystallized source/drain by annealing 233 the amorphous semiconductor layer [0044].
Liu does not explicitly teach a stack of nanostructures. However, in analogous art, Li teaches throughout a stack of nanostructures 207 in place of a single fin as taught by Chen. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Li in order to increase integration of devices which is a constant driving force in semiconductor processing.
Regarding Claim 2, Liu and Li teach the method of claim 1, wherein the annealing the amorphous semiconductor layer includes performing an anneal while an upper surface of amorphous semiconductor layer is exposed ([0041], anneal is simultaneous with silicide formation meaning surface is exposed).
Regarding Claim 3, Liu and Li teach the method of claim 2, wherein the performing an anneal includes performing at least two different anneals (RTA before MLA, [0047]).
Regarding Claim 4, Liu and Li teach the method of claim 2, wherein the performing an anneal terminates after the amorphous semiconductor layer is fully regrown (although not explicit, stopping the anneal when regrowth is complete is implicit and/or inherent as continuing to expend energy on annealing unnecessarily does not stand to reason).
Regarding Claim 5, Liu and Li teach the method of claim 1, wherein the annealing the amorphous semiconductor layer includes annealing the amorphous semiconductor layer after at least one of: forming a contact etch stop layer 296 on the amorphous semiconductor layer; forming an interlayer dielectric 297 on the contact etch stop layer; or forming a replacement gate 228a/b that wraps around the nanostructures of the stack of nanostructures.
Regarding Claim 6, Liu and Li teach the method of claim 5, further comprising performing solid-phase epitaxial regrowth on the amorphous semiconductor layer via a second anneal prior to the annealing the amorphous semiconductor layer (pre MLE RTA process reads on SPER).
Regarding Claim 7, Liu and Li teach the method of claim 6, wherein the performing solid-phase epitaxial regrowth terminates prior to the amorphous semiconductor layer being fully regrown (since both RTA and MLA are described as recrystallizing the S/D, it follows naturally that the initial RTA did not completely recrystallize the S/D ).
Regarding Claim 8, Liu and Li teach a method, comprising:
forming a stack of nanostructures over a substrate;
forming a source/drain opening adjacent the stack of nanostructures;
forming a semiconductor layer in the source/drain opening;
forming an amorphous semiconductor layer by amorphizing the semiconductor layer;
and forming a source/drain by performing solid-phase epitaxy regrowth on the amorphous semiconductor layer (see above rejections of Claims 1-7).
Regarding Claim 9, Liu and Li teach the method of claim 8, wherein the amorphizing the semiconductor layer includes implanting ions, the ions being of a group IV, group III, group V or group VIII species (Germanium, [0012]).
Regarding Claim 10, Liu and Li teach the method of claim 9, wherein the implanting the ions includes implanting the ions at a dosage that exceeds about 1x1013 cm2 [0033].
Regarding Claim 11, Liu and Li teach the method of claim 9, wherein the implanting the ions includes implanting the ions at an energy that is in a range of about 1 kilo-electron-volt (keV) to about 60 keV [0033].
Regarding Claim 12, Liu and Li teach the method of claim 9, wherein the implanting the ions includes implanting the ions at a temperature in a range of about -150 °C to about 500 °C [0033].
Regarding Claim 13, Liu and Li teach the method of claim 8, wherein the performing solid-phase epitaxy regrowth includes performing at least one of rapid thermal annealing (see above), furnace annealing, millisecond annealing, microsecond annealing, flash annealing, laser annealing or melting laser annealing.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Liu and li as applied to claim 21 above, and further in view of U.S. Pat. Pub. No. 20070063306 to Doyle et al. (Doyle).
Regarding Claim 14, Chin and Li teach the method of claim 8, but do not teach performing solid-phase epitaxial regrowth includes performing annealing at a temperature in a range of about 400 °C to about 800 °C for a period in a range of about 10 minutes to about 12 hours.
However, in analogous art, Doyle teaches annealing to recrystallize an amorphized S/D for 10 minutes at 800C [0045]. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Doyle in the event laser or rapid thermal anneal as prescribed by Liu is not available.
Claims 21 rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. 20160056268 to Chin et al. (Chin) in view of Li.
Regarding Claim 21, Chin and Li teach a method, comprising:
forming a stack (see teaching and combination of Li above) of nanostructures (fin showed by Chin) over a substrate;
forming a source/drain opening (where 321 is formed) adjacent the stack of nanostructures;
forming a semiconductor layer 321 in the source/drain opening, the semiconductor layer having stacking faults;
amorphizing 320 the semiconductor layer; and
performing solid-phase epitaxy regrowth to recrystallize the semiconductor layer and eliminate the stacking faults [0037].
Regarding Claim 21, Chin and Li teach the method of claim 21, wherein the performing solid-phase epitaxy regrowth includes annealing at a temperature in a range of about 600°C to about 1200°C [0051].
Regarding Claim 25, Chin and Li teach the method of claim 21, further comprising forming an undoped semiconductor layer in the source/drain opening prior to forming the semiconductor layer (Chin does not teach 321 is doped).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chin and li as applied to claim 21 above, and further in view of U.S. Pat. Pub. No. 20170103977 to Li et al. (Li2).
Regarding Claim 24, Chin and Li teach the method of claim 21, but do not teach forming a bottom insulator in the source/drain opening prior to forming the semiconductor layer.
However, in analogous art, Li2 teaches a bottom insulator 202 under trenches for S/D material to be deposited. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Li2 to prevent stray current.
Allowable Subject Matter
Claims 22 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the cited prior art does not explicitly teach that the stacking faults include (111) direction stacking faults or that the amorphizing the semiconductor layer includes implanting group III ions in a p-type region and implanting group V ions in an n-type region.
Conclusion
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/EVREN SEVEN/Primary Examiner, Art Unit 2812
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